UBA2032TS/N2/N,118 NXP Semiconductors, UBA2032TS/N2/N,118 Datasheet - Page 24

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UBA2032TS/N2/N,118

Manufacturer Part Number
UBA2032TS/N2/N,118
Description
MOSFET & Power Driver ICs Full Bridg Driver IC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of UBA2032TS/N2/N,118

Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
935278859118
NXP Semiconductors
UJA1079_2
Product data sheet
6.10 Temperature protection
6.9 Interrupt output
Pin INTN is an active-LOW, open-drain interrupt output. It is driven LOW when at least
one interrupt is pending. An interrupt can be cleared by writing 1 to the corresponding bit
in the Int_Status register
interrupt status bit and not the pending wake-up. The pending wake-up is cleared on
entering Normal mode and when the corresponding standby control bit (STBCL) is 0.
On devices that contain a watchdog, the Cyclic Interrupt (CI) is enabled when the
watchdog switches to Timeout mode while the SBC is in Standby mode or Normal mode
(provided WDOFF = LOW). A CI is generated if the watchdog overflows in Timeout mode.
The CI is provided to alert the microcontroller when the watchdog overflows in Timeout
mode. The CI will wake up the microcontroller from a μC standby mode. After polling the
Int_Status register, the microcontroller will be aware that the application is in cyclic wake
up mode. It can then perform some checks on LIN before returning to the μC standby
mode.
The temperature of the SBC chip is monitored in Normal and Standby modes. If the
temperature is too high, the SBC will go to Overtemp mode, where the RSTN pin is driven
LOW and limp home is activated. In addition, the voltage regulator and the LIN transmitter
are switched off (see also
below the temperature shutdown threshold, the SBC will go into the Standby mode. The
temperature shutdown threshold is between 165 °C and 200 °C.
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
(Table
Section 6.1.6 “Overtemp
7). Clearing bit LWI in Standby mode only clears the
mode”). When the temperature falls
LIN core system basis chip
UJA1079
© NXP B.V. 2010. All rights reserved.
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