CPC5601D Clare, CPC5601D Datasheet - Page 12

• Manufacturer Part Number: CPC5601D
• Description: IC DRVR PROGRAMMABLE 16-SOIC
• Manufacturer: Clare
• Series: CPCr
• Type: Driverr

Specifications of CPC5601D

• Voltage - Supply: 2.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -

CPC5601
3. Programming
3.1 Latch Circuit Description
Data applied to the input pin is optically coupled to the
shift register through a pulse generator. Each low-to-
high transition in the pulse generator triggers a clock
pulse. Clock pulses are applied to the CLK input of six
3.2 Programming Protocol
Figure 6. Latch Circuit Timing to Turn an Output On
A setup pulse on the input of at least 50 S starts the
bit programming sequence. The trailing edge of the
setup pulse starts a timer on the CPC5601 (t0). After
140 S, the value of the input is latched into the shift
register.
Figure 7. Latch Circuit Timing to Turn an Output Off
To clear an output, hold the input high for 50 S after
the setup pulse, then take the input low for at least 150
12
S.
INPUT (pin 3)
CLOCK
B1 (pin 13)
INPUT (pin 3)
CLOCK
B1 (pin 13)
>=50 s (tsetup)
>=50 s (tsetup)
B1 output FET on (sinking current)
B1 output FET off (drain open)
t0
t0
50 s
Transition after setup time
initiates clock pulse
Transition after setup time
initiates clock pulse
www.clare.com
140 s
140 s
200 s
150 s min
rising-edge-triggered flip-flops. The non-inverted input
data is fed to the flip-flops at all times, but the flip-flops
are only clocked on receipt of a pulse from the pulse
generator. The flip-flops drive six FET switches.
To set an output, hold the input high for 200 S from
the leading edge after the setup pulse. This turns on
the corresponding open-drain FET to sink current.
Repeat the sequence of the setup pulse followed by
the appropriate input condition for each successive bit.
Bear the following in mind while programming the
CPC5601:
thold
B1 output FET on (sinking current)
First flip-flop reads data
at the rising edge of the clock
First flip-flop reads data
at the rising edge of the clock
B1 output FET off (drain open)
R3.0