PIC12F683-I/MD Microchip Technology Inc., PIC12F683-I/MD Datasheet - Page 16
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PIC12F683-I/MD
Manufacturer Part Number
PIC12F683-I/MD
Description
8 PIN, 3.5KB FLASH, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC12F683-IMD.pdf
(148 pages)
Specifications of PIC12F683-I/MD
A/d Inputs
4-Channel, 10-Bit
Comparators
1
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Frequency
20 MHz
Input Output
6
Memory Type
Flash
Number Of Bits
8
Package Type
8-Pin PDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Serial Interface
None
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
PIC12F683-I/MD
Manufacturer:
Cirrus
Quantity:
234
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PIC12F683
2.2.2.4
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
REGISTER 2-4:
DS41211B-page 14
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIE1 Register
PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
bit 7
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
Unimplemented: Read as ‘0’
CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator 1 interrupt
0 = Disables the Comparator 1 interrupt
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the oscillator fail interrupt
0 = disables the oscillator fail interrupt
TMR2IE: Timer 2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer 2 to PR2 match interrupt
0 = Disables the Timer 2 to PR2 match interrupt
TMR1IE: Timer 1 Overflow Interrupt Enable bit
1 = Enables the Timer 1 overflow interrupt
0 = Disables the Timer 1 overflow interrupt
Legend:
R = Readable bit
- n = Value at POR
R/W-0
EEIE
R/W-0
ADIE
CCP1IE
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
U-0
—
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CMIE
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
OSFIE
R/W-0
2004 Microchip Technology Inc.
x = Bit is unknown
TMR2IE
R/W-0
TMR1IE
R/W-0
bit 0
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