PIC16F1947-I/PT Microchip Technology Inc., PIC16F1947-I/PT Datasheet - Page 214

• Manufacturer Part Number: PIC16F1947-I/PT
• Description: 64 TQFP 10x10x1mm TRAY28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1947-I/PT

• A/d Inputs: 17-Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 54
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 28K Bytes
• Ram Size: 1K Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F/LF1946/47
23.1
The Capture mode function described in this section is
available and identical for CCP modules ECCP1,
ECCP2, ECCP3, CCP4 and CCP5.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCPx pin, the
16-bit CCPRxH:CCPRxL register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
Figure 23-1
operation.
23.1.1
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Also, the CCPx pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function”
details.
FIGURE 23-1:
DS41414B-page 214
CCPx
pin
Note:
System Clock (F
Capture Mode
Edge Detect
CCP PIN CONFIGURATION
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
Prescaler
 1, 4, 16
shows a simplified diagram of the Capture
and
CCPxM<3:0>
OSC
)
Set Flag bit CCPxIF
(PIRx register)
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Capture
Enable
CCPRxH
TMR1H
CCPRxL
for more
TMR1L
Preliminary
23.1.2
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
See
for more information on configuring Timer1.
23.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in Operating mode.
23.1.4
There are four prescaler settings specified by the
CCPxM<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler.
perform this function.
EXAMPLE 23-1:
BANKSEL CCPxCON
CLRF
MOVLW
MOVWF
Note:
Section 21.0 “Timer1 Module with Gate Control”
CCPxCON
NEW_CAPT_PS ;Load the W reg with
CCPxCON
Example 23-1
TIMER1 MODE RESOURCE
SOFTWARE INTERRUPT MODE
Clocking Timer1 from the system clock
(F
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1 must be clocked from the
instruction clock (F
external clock source.
CCP PRESCALER
OSC
) should not be used in Capture
CHANGING BETWEEN
CAPTURE PRESCALERS
;Set Bank bits to point
;to CCPxCON
;Turn CCP module off
;the new prescaler
;move value and CCP ON
;Load CCPxCON with this
;value
 2010 Microchip Technology Inc.
demonstrates the code to
OSC
/4) or from an