PIC18F26K80-I/SO Microchip Technology Inc., PIC18F26K80-I/SO Datasheet - Page 74
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PIC18F26K80-I/SO
Manufacturer Part Number
PIC18F26K80-I/SO
Description
IC, MCU, nanoWatt; 8-bit w/ECAN; Flash, 64KB; 16MIPS; 8-ch, 12-BIT A/D; SOIC-28
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/SO
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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PIC18F66K80 FAMILY
4.4.3
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode
provides controllable power conservation during Idle
periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. To maintain software
compatibility with future devices, it is recommended
that SCS0 also be cleared, though its value is ignored.
The INTOSC multiplexer may be used to select a
higher clock frequency by modifying the IRCF bits
before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC/MFIOSEL bit is set, the INTOSC output is
enabled. The HFIOFS/MFIOFS bits become set, after
the INTOSC output becomes stable, after an interval of
T
the HFIOFS/MFIOFS bits, see
Clocks to the peripherals continue while the INTOSC
source stabilizes. The HFIOFS/MFIOFS bits will
remain set if the IRCF bits were previously at a non-
zero value or if INTSRC was set before the SLEEP
instruction was executed and the INTOSC source was
already stable. If the IRCF bits and INTSRC are all
clear, the INTOSC output will not be enabled, the
HFIOFS/MFIOFS bits will remain clear and there will be
no indication of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
of T
event, the CPU begins executing code clocked by the
INTOSC multiplexer. The IDLEN and SCS bits are not
affected by the wake-up. The INTOSC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
DS39977C-page 74
IOBST
CSD
(Parameter 38,
(Parameter 38,
RC_IDLE MODE
Table
Table
31-11). For information on
31-11) following the wake
Table
4-3.
Preliminary
4.5
Idle mode allows users to substantially reduce power
consumption by stopping the CPU clock. Even so,
peripheral modules still remain clocked, and thus, con-
sume power. There may be cases where the application
needs what this mode does not provide: the allocation of
power resources to the CPU processing with minimal
power consumption from the peripherals.
PIC18F66K80 family devices address this requirement
by allowing peripheral modules to be selectively
disabled,
consumption. This can be done with two control bits:
• Peripheral Enable bit, generically named XXXEN –
• Peripheral Module Disable (PMD) bit, generically
Disabling a module by clearing its XXXEN bit disables
the module’s functionality, but leaves its registers
available to be read and written to. This reduces power
consumption, but not by as much as the second
approach.
Most peripheral modules have an enable bit.
In contrast, setting the PMD bit for a module disables
all clock sources to that module, reducing its power
consumption to an absolute minimum. In this state, the
control and status registers associated with the periph-
eral are also disabled, so writes to those registers have
no effect and read values are invalid. Many peripheral
modules have a corresponding PMD bit.
There are three PMD registers in PIC18F66K80 family
devices: PMD0, PMD1 and PMD2. These registers
have bits associated with each module for disabling or
enabling a particular peripheral.
Located in the respective module’s main control
register
named, XXXMD – Located in one of the PMDx
Control registers (PMD0, PMD1 or PMD2)
Selective Peripheral Module
Control
reducing
or
2011 Microchip Technology Inc.
eliminating
their
power
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