DSPIC30F2012-30I/SP Microchip Technology Inc., DSPIC30F2012-30I/SP Datasheet - Page 75
DSPIC30F2012-30I/SP
Manufacturer Part Number
DSPIC30F2012-30I/SP
Description
DSP, 16-Bit, 12 KB Flash, 1KB RAM, 20 I/O, PDIP-28
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F2012-30ISP.pdf
(205 pages)
Specifications of DSPIC30F2012-30I/SP
A/d Inputs
10-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
0 Bytes
Input Output
20
Interface
I2C, SPI, UART/USART
Ios
20
Memory Type
Flash
Number Of Bits
16
Package Type
28-pin SPDIP
Programmable Memory
12K Bytes
Ram Size
1K Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Manufacturer
Quantity
Price
Part Number:
DSPIC30F2012-30I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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9.5.1
When the TON = 1, TCS = 1 and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP oscilla-
tor output signal, up to the value specified in the Period
register and is then reset to ‘0’.
The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) disables the
normal Timer and Counter modes and enables a timer
carry-out wake-up event.
When the CPU enters Sleep mode, the RTC continues
to operate, provided the 32 kHz external crystal oscilla-
tor is active and the control bits have not been
changed. The TSIDL bit should be cleared to ‘0’ in
order for RTC to continue operation in Idle mode.
© 2006 Microchip Technology Inc.
RTC OSCILLATOR OPERATION
dsPIC30F2011/2012/3012/3013
9.5.2
When an interrupt event occurs, the respective interrupt
flag, T1IF, is asserted and an interrupt is generated if
enabled. The T1IF bit must be cleared in software. The
respective Timer interrupt flag, T1IF, is located in the
IFS0 register in the interrupt controller.
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.
RTC INTERRUPTS
DS70139E-page 73
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