PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet - Page 131

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PIC16F72-I/SP

Manufacturer Part Number
PIC16F72-I/SP
Description
28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F72-I/SP

A/d Inputs
5-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
22
Interface
I2C/SPI
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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Timing Diagrams
Timing Parameter Symbology............................................. 93
TMR1H Register ................................................................... 9
TMR1L Register .................................................................... 9
TMR2 Register ...................................................................... 9
TMR2ON bit ........................................................................ 36
TOUTPS0 bit....................................................................... 36
TOUTPS1 bit....................................................................... 36
TOUTPS2 bit....................................................................... 36
TOUTPS3 bit....................................................................... 36
TRISA Register ............................................................. 10, 21
TRISB Register ............................................................. 10, 23
TRISC Register ............................................................. 10, 25
2002 Microchip Technology Inc.
A/D Conversion......................................................... 105
Brown-out Reset ......................................................... 96
Capture/Compare/PWM (CCP1)................................. 98
CLKO and I/O ............................................................. 95
External Clock............................................................. 94
I
I
I
I
RESET, Watchdog Timer, Oscillator Start-up Timer
Slow Rise Time (MCLR Tied to V
SPI Master Mode ........................................................ 47
SPI Master Mode (CKE = 0, SMP = 0) ....................... 99
SPI Master Mode (CKE = 1, SMP = 1) ....................... 99
SPI Slave Mode (CKE = 0) ................................. 47, 100
SPI Slave Mode (CKE = 1) ................................. 47, 100
Time-out Sequence on Power-up (MCLR Tied to
Time-out Sequence on Power-up (MCLR Tied to
Time-out Sequence on Power-up (MCLR Tied to
Timer0 and Timer1 External Clock.............................. 97
Wake-up from SLEEP through Interrupt ..................... 72
2
2
2
2
C Bus Data ............................................................. 102
C Bus START/STOP bits........................................ 101
C Reception (7-bit Address) ..................................... 50
C Transmission (7-bit Address) ................................ 50
and Power-up Timer............................................... 96
RC Network)........................................................... 68
V
V
V
DD
DD
DD
Through Pull-up Resistor)............................... 67
Through RC Network): Case 1 ....................... 67
Through RC Network): Case 2 ....................... 67
DD
Through
U
UA....................................................................................... 44
Update Address bit, UA ...................................................... 44
W
Wake-up from SLEEP................................................... 59, 71
Watchdog Timer (WDT)................................................ 59, 70
WCOL ................................................................................. 45
Write Collision Detect bit, WCOL........................................ 45
WWW, On-Line Support ....................................................... 3
Interrupts .............................................................. 65, 66
MCLR Reset ............................................................... 66
WDT Reset ................................................................. 66
Associated Registers.................................................. 70
Enable (WDTEN bit) ................................................... 70
Postscaler. See Postscaler, WDT
Programming Considerations ..................................... 70
RC Oscillator .............................................................. 70
Time-out Period .......................................................... 70
WDT Reset, Normal Operation....................... 62, 65, 66
WDT Reset, SLEEP ....................................... 62, 65, 66
PIC16F72
DS39597B-page 129

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