PIC16F916-I/SP Microchip Technology Inc., PIC16F916-I/SP Datasheet - Page 177
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PIC16F916-I/SP
Manufacturer Part Number
PIC16F916-I/SP
Description
28 PIN, 14 KB FLASH, 352 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F916-ISP.pdf
(272 pages)
Specifications of PIC16F916-I/SP
A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
14K Bytes
Ram Size
352 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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14.13 Master Mode
Master mode of operation is supported in firmware
using interrupt generation on the detection of the Start
and Stop conditions. The Stop (P) and Start (S) bits are
cleared from a Reset or when the SSP module is dis-
abled. The Stop (P) and Start (S) bits will toggle based
on the Start and Stop conditions. Control of the I
may be taken when the P bit is set or the bus is idle and
both the S and P bits are clear.
In Master mode, the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<6:7> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<6:7>. So when transmitting data, a
‘1’ data bit must have the TRISC<7> bit set (input) and
a ‘0’ data bit must have the TRISC<7> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<6> bit. Pull-up resistors must be provided
externally to the SCL and SDA pins for proper opera-
tion of the I
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt will occur if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode idle (SSPM<3:0> = 1011), or with the
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
© 2005 Microchip Technology Inc.
2
C module.
2
C bus
Preliminary
PIC16F917/916/914/913
14.14 Multi-Master Mode
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions, allows the
determination of when the bus is free. The Stop (P)
and Start (S) bits are cleared from a Reset or when the
SSP module is disabled. The Stop (P) and Start (S)
bits will toggle based on the Start and Stop conditions.
Control of the I
(SSPSTAT<4>) is set, or the bus is idle and both the S
and P bits clear. When the bus is busy, enabling the
SSP Interrupt will generate the interrupt when the Stop
condition occurs.
In Multi-Master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISC<6:7>). There are two
stages where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues
to receive. If arbitration was lost during the address
transfer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
14.14.1
When the CKP bit is cleared, the SCL output is forced
to ‘0’; however, setting the CKP bit will not assert the
SCL output low until the SCL output is already sampled
low. Therefore, the CKP bit will not assert the SCL line
until an external I
asserted the SCL line. The SCL output will remain low
until the CKP bit is set and all other devices on the I
bus have deasserted SCL. This ensures that a write to
the CKP bit will not violate the minimum high time
requirement for SCL (see Figure 14-12).
CLOCK SYNCHRONIZATION AND
THE CKP BIT
2
C bus may be taken when bit P
2
C master device has already
DS41250E-page 175
2
C
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