PIC16F916-I/SP Microchip Technology Inc., PIC16F916-I/SP Datasheet - Page 102
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC16F916-I/SP
Manufacturer Part Number
PIC16F916-I/SP
Description
28 PIN, 14 KB FLASH, 352 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F916-ISP.pdf
(272 pages)
Specifications of PIC16F916-I/SP
A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
14K Bytes
Ram Size
352 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F916-I/SP
Manufacturer:
Microchip Technology
Quantity:
1 800
Company:
Part Number:
PIC16F916-I/SP
Manufacturer:
JST
Quantity:
4 300
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PIC16F917/916/914/913
REGISTER 8-3:
TABLE 8-2:
DS41250E-page 100
0Bh/8Bh
0Dh
9Ch
97h
85h
8Dh
9Dh
Legend:
Address
INTCON
PIR2
CMCON0
CMCON1
TRISA
PIE2
VRCON
bit 7
bit 6
bit 5
bit 4
bit 3-0
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator or Comparator Voltage
Reference module.
Name
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
C2OUT
TRISA7
OSFIF
OSFIE
VREN
VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 9Dh)
Bit 7
bit 7
GIE
VREN: CV
1 = CV
0 = CV
Unimplemented: Read as ‘0’
VRR: CV
1 = Low range
0 = High range
Unimplemented: Read as ‘0’
VR<3:0>: CV
When VRR = 1: CV
When VRR = 0: CV
Legend:
R = Readable bit
- n = Value at POR
—
R/W-0
VREN
REF
REF
C1OUT
TRISA6
Bit 6
PEIE
C2IF
C2IE
REF
—
—
REF
circuit powered on
circuit powered down, no I
Range Selection bit
REF
Enable bit
U-0
—
TRISA5
C2INV
C1IE
Bit 5
T0IE
C1IF
VRR
value selection 0
—
REF
REF
= (VR<3:0>/24) * V
= V
TRISA4
R/W-0
LCDIF
C1INV
LCDIE
Bit 4
INTE
VRR
DD
Preliminary
—
—
W = Writable bit
‘1’ = Bit is set
/4 + (VR<3:0>/32) * V
TRISA3
RBIE
Bit 3
VR3
CIS
—
—
—
DD
R/W-0
VR<3:0>
—
drain and CV
DD
TRISA2
LVDIF
LVDIE
Bit 2
T0IF
CM2
VR2
—
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
15
VR3
DD
TRISA1
T1GSS
Bit 1
INTF
CM1
VR1
REF
—
—
= V
C2SYNC
R/W-0
CCP2IE
CCP2IF
TRISA0
SS
VR2
RBIF
Bit 0
CM0
VR0
© 2005 Microchip Technology Inc.
.
0000 000x
0000 -0-0
0000 0000
---- --10
1111 1111
0000 -0-0
0-0- 0000
POR, BOR
Value on
x = Bit is unknown
R/W-0
VR1
0000 000x
0000 -0-0
0000 0000
---- --10
1111 1111
0000 -0-0
0-0- 0000
Value on
all other
R/W-0
Resets
VR0
bit 0
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