PIC16F737-I/SO Microchip Technology Inc., PIC16F737-I/SO Datasheet - Page 160

• Manufacturer Part Number: PIC16F737-I/SO
• Description: MCU, 8-Bit, 4KW Flash, 368 RAM, 25 I/O, SOIC-28
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SO

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X7
12.4
The selection of the automatic acquisition time and
A/D conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a
(ADCON2<5:3>) and ADCS2:ADCS0 (ADCON1<6>,
ADCON0<7:6>) bits should be updated in accordance
with the power-managed mode clock that will be used.
After the power-managed mode is entered (either of
the power-managed Run modes), an A/D acquisition or
conversion may be started. Once an acquisition or
conversion is started, the device should continue to be
clocked by the same power-managed mode clock
source until the conversion has been completed.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits ACQT2:ACQT0 are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode.
DS30498C-page 158
power-managed
Operation in Power-Managed
Modes
mode,
the
ACQT2:ACQT0
12.5
The ADCON1, TRISA, TRISB and TRISE registers
control the operation of the A/D port pins. The port pins
that are desired as analog inputs must have their
corresponding TRIS bits set (input). If the TRIS bit is
cleared (output), the digital output level (V
will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the Port register, all pins
2: Analog levels on any pin that is defined as
Configuring Analog Port Pins
configured as analog input channels will
read as cleared (a low level). Pins con-
figured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
a digital input, but not as an analog input,
may cause the digital input buffer to
consume current that is out of the
device’s specification.
 2004 Microchip Technology Inc.
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