PIC18F6680-I/PT Microchip Technology Inc., PIC18F6680-I/PT Datasheet - Page 310
PIC18F6680-I/PT
Manufacturer Part Number
PIC18F6680-I/PT
Description
64 PIN, 64 KB FLASH, 3328 RAM, 52 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F6680-IPT.pdf
(396 pages)
Specifications of PIC18F6680-I/PT
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
53
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
64-pin TQFP
Programmable Memory
64K Bytes
Ram Size
3.3K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6680-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F6525/6621/8525/8621
RLNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39612B-page 308
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
=
=
register ‘f’
Rotate Left f (No Carry)
[ label ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n + 1>;
(f<7>) → dest<0>
N, Z
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
1
1
RLNCF
Read
Q2
0100
1010 1011
0101 0111
RLNCF
01da
Process
REG, 1, 0
Data
Q3
register f
f [,d [,a]
ffff
destination
Write to
Q4
ffff
RRCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register ‘f’
Rotate Right f through Carry
[ label ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n – 1>;
(f<0>) → C;
(C) → dest<7>
C, N, Z
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is ‘1’, then
the bank will be selected as per the
BSR value (default).
1
1
RRCF
Read
0011
Q2
1110 0110
0
1110 0110
0111 0011
0
2005 Microchip Technology Inc.
C
RRCF
00da
Process
REG, 0, 0
Data
register f
Q3
f [,d [,a]
ffff
destination
Write to
Q4
ffff
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