PIC18F4220-I/P Microchip Technology Inc., PIC18F4220-I/P Datasheet - Page 344
PIC18F4220-I/P
Manufacturer Part Number
PIC18F4220-I/P
Description
Microcontroller; 4 KB Flash; 512 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4220-IP.pdf
(388 pages)
Specifications of PIC18F4220-I/P
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
4K Bytes
Ram Size
512 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
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SST
Quantity:
1 150
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Part Number:
PIC18F4220-I/PT
Manufacturer:
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PIC18F2220/2320/4220/4320
FIGURE 26-23:
TABLE 26-25: A/D CONVERSION REQUIREMENTS
DS39599C-page 342
130
131
Note 1:
Param
No.
Note 1: If the A/D clock source is selected as RC, a time of T
A/D DATA
SAMPLE
A/D CLK
2:
ADRES
BSF ADCON0, GO
T
T
Symbol
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
ADIF
AD
CNV
GO
Q4
ADRES register may be read on the following T
The time of the A/D clock period is dependent on the device frequency and the T
executed.
132
A/D Clock Period
Conversion Time
(not including acquisition time)
A/D CONVERSION TIMING
(Note 2)
Characteristic
9
8
PIC18FXX20
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
OLD_DATA
7
(1)
CY
. . .
SAMPLING STOPPED
is added before the A/D clock starts. This allows the SLEEP instruction to be
CY
. . .
131
130
cycle.
Min
1.6
3.0
2.0
3.0
11
2
20
20
Max
6.0
9.0
12
1
(2)
(2)
Units
T
AD
s
s
s
s
0
2003 Microchip Technology Inc.
T
T
A/D RC mode
A/D RC mode
OSC
OSC
AD
based, V
based, V
clock divider.
NEW_DATA
DONE
Conditions
T
CY
REF
REF
full range
3.0V
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