PIC18F4220-I/P Microchip Technology Inc., PIC18F4220-I/P Datasheet - Page 226
PIC18F4220-I/P
Manufacturer Part Number
PIC18F4220-I/P
Description
Microcontroller; 4 KB Flash; 512 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4220-IP.pdf
(388 pages)
Specifications of PIC18F4220-I/P
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
4K Bytes
Ram Size
512 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F2220/2320/4220/4320
FIGURE 20-3:
20.6
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the Comparator Interrupt Flag. The
CMIF bit is cleared by firmware. Since it is also possible
to write a ‘1’ to this register, a simulated interrupt may
be initiated.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
DS39599C-page 224
Comparator Interrupts
COMPARATOR OUTPUT BLOCK DIAGRAM
To RA4 or
RA5 Pin
Bus
Data
Set
CMIF
bit
Read CMCON
From
other
Comparator
Q
Q
EN
D
CL
EN
D
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
Note:
Reset
Any read or write of CMCON will end the
mismatch condition.
Clear flag bit CMIF.
Read CMCON
MULTIPLEX
Port Pins
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
+
-
2003 Microchip Technology Inc.
CxINV
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