PIC16C74B-20/P Microchip Technology Inc., PIC16C74B-20/P Datasheet - Page 31

• Manufacturer Part Number: PIC16C74B-20/P
• Description: 40 PIN, 7 KB OTP, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C74B-20/P

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 4 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.2
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 5-3:
Four
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the value latched on the
last read of PORTB. The “mismatch” outputs of
RB7:RB4 are OR’d together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON<0>).
Note 1: I/O pins have diode protection to V
2000 Microchip Technology Inc.
RBPU
Data Bus
WR Port
WR TRIS
RB0/INT
of
2: To enable weak pull-ups, set the appropriate TRIS
(2)
PORTB and TRISB Registers
bit(s) and clear the RBPU bit (OPTION_REG<7>).
PORTB’s
RD TRIS
RD Port
Data Latch
TRIS Latch
D
D
CK
CK
Schmitt Trigger
Buffer
BLOCK DIAGRAM OF
RB3:RB0 PINS
pins,
Q
Q
RB7:RB4,
Q
EN
TTL
Input
Buffer
DD
D
and V
V
P
RD Port
DD
have
SS
I/O pin
Weak
Pull-up
.
(1)
an
PIC16C63A/65B/73B/74B
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt-on-mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Stroke” (AN552).
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
RB0/INT is discussed in detail in Section 13.5.1.
FIGURE 5-4:
From other
RB7:RB4 pins
Set RBIF
RBPU
Data Bus
WR Port
WR TRIS
RB7:RB6 in Serial Programming mode
Note 1: I/O pins have diode protection to V
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
(2)
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
RD TRIS
RD Port
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
BLOCK DIAGRAM OF
RB7:RB4 PINS
Q
Q
Latch
EN
EN
D
D
DS30605C-page 31
TTL
Input
Buffer
DD
V
and V
P
DD
Weak
Pull-up
RD Port
I/O pin
Buffer
SS
Q1
Q3
.
ST
(1)