PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 92

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 8-1:
EXAMPLE 8-3:
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pair’s Most Significant bit (MSb)
is tested, and the appropriate subtractions are done.
DS39616B-page 90
RES3:RES0
;
;
;
MOVFARG1L, W
MULWFARG2L
MOVFFPRODH, RES1
MOVFFPRODL, RES0
MOVFARG1H, W
MULWFARG2H
MOVFFPRODH, RES3
MOVFFPRODL, RES2
MOVFARG1L, W
MULWFARG2H
MOVFPRODL, W
ADDWFRES1, F
MOVFPRODH, W
ADDWFCRES2, F
CLRFWREG
ADDWFCRES3, F
MOVFARG1H, W
MULWFARG2L
MOVFPRODL, W
ADDWFRES1, F
MOVFPRODH, W
ADDWFCRES2, F
CLRFWREG
ADDWFCRES3, F
=
=
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 2
(ARG1H ARG2L 2
(ARG1L ARG2H 2
(ARG1L ARG2L)
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
16 x 16 UNSIGNED
MULTIPLY ROUTINE
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
8
8
16
)+
)+
)+
Preliminary
EQUATION 8-2:
EXAMPLE 8-4:
RES3:RES0
;
;
;
;
;
SIGN_ARG1
;
CONT_CODE
:
=
=
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC RES2,
CLRF
ADDWFC RES3,
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC RES2,
CLRF
ADDWFC RES3,
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB RES3
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB RES3
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 2
(ARG1H ARG2L 2
(ARG1L ARG2H ² 2
(ARG1L ARG2L)+
(-1 ARG2H<7> ARG1H:ARG1L 2
(-1 ARG1H<7> ARG2H:ARG2L 2
ARG1L, W
ARG2L
PRODH, RES1 ;
PRODL, RES0 ;
ARG1H, W
ARG2H
PRODH, RES3 ;
PRODL, RES2 ;
ARG1L, W
ARG2H
PRODL, W
RES1,
PRODH, W
WREG
ARG1H, W
ARG2L
PRODL, W
RES1,
PRODH, W
WREG
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
16 x 16 SIGNED
MULTIPLY ROUTINE
 2003 Microchip Technology Inc.
F
F
F
F
F
F
; ARG1L * ARG2L ->
; PRODH:PRODL
; ARG1H * ARG2H ->
; PRODH:PRODL
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
; ARG1H:ARG1L neg?
; no, done
;
;
;
8
8
16
)+
)+
)+
16
16
)+
)