PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 120
PIC18F2431-I/SP
Manufacturer Part Number
PIC18F2431-I/SP
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2431-ISP.pdf
(396 pages)
Specifications of PIC18F2431-I/SP
A/d Inputs
5-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2431-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18F2331/2431/4331/4431
10.3
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). The pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
FIGURE 10-13:
DS39616B-page 118
Note:
T1 Clock Input
PORTC, TRISC and LATC
Registers
T1 OSC EN
WR TRISC
RD PORTC
WR LATC
On a Power-on Reset, these pins are
configured as digital inputs.
Data Bus
PORTC
or
BLOCK DIAGRAM OF RC0
TRIS Latch
Data Latch
D
D
RD TRISC
RD LATC
CK
CK
Q
Q
Q
Q
Preliminary
Q
EN
External interrupts, IN0, INT1 and INT2, are placed on
RC3, RC4 and RC5 respectively.
SSP alternate interface pins, SDI/SDA, SCK/SCL and
SDO are placed on RC4, RC5, and RC7 pins respec-
tively.
These pins are multiplexed on PORTC and PORTD by
using the SSPMX bit in the CONFIG3L register.
USART pins RX/DT and TX/CK are placed on RC7 and
RC6 respectively.
The alternate Timer5 external clock input, T5CKI, and
the alternate TMR0 external clock input, T0CKI, are
placed on RC3 and are multiplexed with the PORTD
(RD0) pin using the EXCLKMX configuration bit in
CONFIG3L. Fault inputs to the 14-bit PWM module,
FLTA and FLTB, are located on RC1 and RC2. FLTA
input on RC1 is multiplexed with RD4 using the
FLTAMX bit.
EXAMPLE 10-3:
D
CLRF
CLRF
MOVLW
MOVWF
V
V
N
PORTC
LATC
0xCF
TRISC
P
SS
DD
Schmitt
Trigger
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
INITIALIZING PORTC
2003 Microchip Technology Inc.
Timer1
Oscillator
RC0 Pin
To RC1 Pin
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