PIC18F24J10-I/SS Microchip Technology Inc., PIC18F24J10-I/SS Datasheet - Page 266
PIC18F24J10-I/SS
Manufacturer Part Number
PIC18F24J10-I/SS
Description
Microcontroller; 16 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-SSOP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F24J10-ISS.pdf
(359 pages)
Specifications of PIC18F24J10-I/SS
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SSOP
Programmable Memory
16K Bytes
Ram Size
1K Bytes
Speed
40 MHz
Timers
1-8-bit, 2-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F24J10-I/SS
Manufacturer:
MICROCHIP
Quantity:
1 667
Part Number:
PIC18F24J10-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 266 of 359
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39682B-page 264
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
Inclusive OR Literal with W
IORLW k
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
1
1
IORLW
literal ‘k’
Read
0000
Q2
9Ah
BFh
1001
35h
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
Preliminary
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
RESULT =
W
RESULT =
W
Q1
=
=
register ‘f’
Inclusive OR W with f
IORWF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .OR. (f) → dest
N, Z
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
IORWF
Read
0001
Q2
13h
91h
13h
93h
© 2006 Microchip Technology Inc.
RESULT, 0, 1
f {,d {,a}}
00da
Process
Data
Q3
ffff
destination
Write to
Q4
ffff
Related parts for PIC18F24J10-I/SS
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet:
Part Number:
Description:
Manufacturer:
Microchip Technology Inc.
Datasheet: