PIC18F24J10-I/SS Microchip Technology Inc., PIC18F24J10-I/SS Datasheet - Page 250
PIC18F24J10-I/SS
Manufacturer Part Number
PIC18F24J10-I/SS
Description
Microcontroller; 16 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-SSOP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F24J10-ISS.pdf
(359 pages)
Specifications of PIC18F24J10-I/SS
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SSOP
Programmable Memory
16K Bytes
Ram Size
1K Bytes
Speed
40 MHz
Timers
1-8-bit, 2-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F24J10-I/SS
Manufacturer:
MICROCHIP
Quantity:
1 667
Part Number:
PIC18F24J10-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18F45J10 FAMILY
ADDWFC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39682B-page 248
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Carry bit
REG
W
Carry bit
REG
W
Q1
register ‘f’
=
=
=
=
=
=
ADD W and Carry bit to f
ADDWFC
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + (f) + (C) → dest
N,OV, C, DC, Z
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
ADDWFC
Read
0010
Q2
1
02h
4Dh
0
02h
50h
00da
f {,d {,a}}
REG, 0, 1
Process
Data
Q3
ffff
destination
Write to
Q4
ffff
Preliminary
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
Read literal
AND Literal with W
ANDLW
0 ≤ k ≤ 255
(W) .AND. k → W
N, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
1
1
ANDLW
0000
Q2
‘k’
A3h
03h
© 2006 Microchip Technology Inc.
k
1011
05Fh
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
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