PIC16C711-04/P Microchip Technology Inc., PIC16C711-04/P Datasheet - Page 63

• Manufacturer Part Number: PIC16C711-04/P
• Description: 18 PIN, 1.75 KB OTP, 68 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C711-04/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 68 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.5.1
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 8.8 for details on SLEEP mode.
FIGURE 8-19: INT PIN INTERRUPT TIMING
1997 Microchip Technology Inc.
INSTRUCTION FLOW
Note 1: INTF flag is sampled here (every Q1).
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
executed
Instruction
fetched
PC
2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
INT INTERRUPT
on
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3
the
Q1
Inst (PC-1)
RB0/INT
Inst (PC)
1
Q2
PC
Q3
4
pin,
Q4
5
Q1
flag
Inst (PC+1)
Inst (PC)
Q2
1
bit
PC+1
Q3
INTF
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
8.5.2
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 6.0)
8.5.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
PC+1
—
Note:
Q3
Q4
TMR0 INTERRUPT
PORTB INTCON CHANGE
2
For the PIC16C71
if a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
00h) in the TMR0 register will set
Q3
PIC16C71X
Q4
Q1
DS30272A-page 63
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4