PIC17C756A-16I/L Microchip Technology Inc., PIC17C756A-16I/L Datasheet - Page 134
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PIC17C756A-16I/L
Manufacturer Part Number
PIC17C756A-16I/L
Description
68 PIN, 32 KB OTP, 902 RAM, 50 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC17C756A-16IL.pdf
(304 pages)
Specifications of PIC17C756A-16I/L
A/d Inputs
12-Channel, 10-Bit
Cpu Speed
8.25 MIPS
Eeprom Memory
0 Bytes
Input Output
52
Interface
I2C/SPI/USART
Memory Type
OTP
Number Of Bits
8
Package Type
68-pin PLCC
Programmable Memory
32K Bytes
Ram Size
902 Bytes
Speed
16 MHz
Timers
2-8-bit, 2-16-bit
Voltage, Range
3-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756A-16I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC17C756A-16I/L
Manufacturer:
MICROCH
Quantity:
20 000
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PIC17C7XX
REGISTER 15-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 13h, BANK 6)
DS30289B-page 134
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High Speed mode (400 kHz)
CKE: SPI Clock Edge Select (Figure 15-6, Figure 15-8 and Figure 15-9)
CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: STOP bit
(I
1 = Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0 = STOP bit was not detected last
S: START bit
(I
1 = Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0 = START bit was not detected last
R/W: Read/Write bit Information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or not ACK bit.
In I
1 = Read
0 = Write
In I
1 = Transmit is in progress
0 = Transmit is not in progress
Or’ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
- n = Value at POR Reset
R/W-0
2
2
SMP
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
2
2
2
C Master or Slave mode:
C Slave mode:
C Master mode:
2
C mode only)
R/W-0
CKE
2
C modes)
2
C mode only)
R-0
D/A
W = Writable bit
’1’ = Bit is set
2
C mode only)
2
C mode only)
R-0
P
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R-0
S
R/W
R-0
2000 Microchip Technology Inc.
x = Bit is unknown
R-0
UA
R-0
BF
bit 0
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