PIC17C756A-16I/L Microchip Technology Inc., PIC17C756A-16I/L Datasheet - Page 133
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PIC17C756A-16I/L
Manufacturer Part Number
PIC17C756A-16I/L
Description
68 PIN, 32 KB OTP, 902 RAM, 50 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC17C756A-16IL.pdf
(304 pages)
Specifications of PIC17C756A-16I/L
A/d Inputs
12-Channel, 10-Bit
Cpu Speed
8.25 MIPS
Eeprom Memory
0 Bytes
Input Output
52
Interface
I2C/SPI/USART
Memory Type
OTP
Number Of Bits
8
Package Type
68-pin PLCC
Programmable Memory
32K Bytes
Ram Size
902 Bytes
Speed
16 MHz
Timers
2-8-bit, 2-16-bit
Voltage, Range
3-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756A-16I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC17C756A-16I/L
Manufacturer:
MICROCH
Quantity:
20 000
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15.0
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit
Figure 15-1 shows a block diagram for the SPI mode,
while Figure 15-2 and Figure 15-3 show the block
diagrams for the two different I
FIGURE 15-1:
2000 Microchip Technology Inc.
SDO
SCK
SDI
SS
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Read
SS Control
SMP:CKE
Select
Edge
Enable
bit0
Select
Edge
SSPBUF reg
SPI MODE BLOCK
DIAGRAM
Data to TX/RX in SSPSR
Data Direction bit
2
SSPSR reg
TM
SSPM3:SSPM0
Clock Select
(I
4
2
C)
2
C modes of operation.
2
Write
Prescaler
4, 16, 64
Clock
Shift
TMR2 Output
Data Bus
Internal
2
Tosc
FIGURE 15-2:
FIGURE 15-3:
SDA
SCL
SDA
SCL
Baud Rate Generator
SSPADD<6:0>
7
Read
Read
Clock
Clock
Shift
Shift
START and STOP bit
MSb
MSb
Detect/Generate
STOP bit Detect
I
DIAGRAM
I
BLOCK DIAGRAM
2
Match Detect
2
SSPADD reg
SSPADD reg
SSPBUF reg
SSPBUF reg
Match detect
START and
SSPSR reg
SSPSR reg
PIC17C7XX
C SLAVE MODE BLOCK
C MASTER MODE
LSb
LSb
DS30289B-page 133
Write
Write
(SSPSTAT reg)
(SSPSTAT reg)
Clear/Set P, bit
and Set SSPIF
Set/Clear S bit
Data Bus
Data Bus
Internal
Internal
Call Detected
Call Detected
Set, Reset
S, P bits
Addr Match
Addr Match
or General
or General
and
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