PIC12C509A-04/P Microchip Technology Inc., PIC12C509A-04/P Datasheet - Page 72

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PIC12C509A-04/P

Manufacturer Part Number
PIC12C509A-04/P
Description
8 PIN, 1.5 KB OTP, 41 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC12C509A-04/P

Cpu Speed
1 MIPS
Eeprom Memory
0 Bytes
Input Output
5
Memory Capacity
1024 Bytes
Memory Type
OTP
Number Of Bits
8
Number Of Leads
6
Package Type
8-pin PDIP
Programmable Memory
1.5K Bytes
Ram Size
41 Bytes
Speed
4 MHz
Timers
1-8-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC12C5XX
TABLE 11-4:
FIGURE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12C508/C509
DS40139E-page 72
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Parameter
Watchdog
AC Characteristics
Timeout
(Note 2)
2: Measurements are taken in EXTRC mode.
3: See Figure 11-1 for loading conditions.
Internal
Internal
RESET
RESET
I/O pin
(Note 1)
No.
17
18
19
20
21
MCLR
Timer
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
POR
DRT
V
guidance only and are not tested.
DD
2: Runs in MCLR or WDT reset only in XT and LP modes.
TosH2ioV
TosH2ioI
TioV2osH
TioR
TioF
TIMING REQUIREMENTS - PIC12C508/C509
Sym
32
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
Operating Voltage V
OSC1 (Q1 cycle) to Port out valid
OSC1 (Q2 cycle) to Port input invalid
(I/O in hold time)
Port input valid to OSC1
(I/O in setup time)
Port output rise time
Port output fall time
Characteristic
(2, 3)
DD
(2, 3)
34
range is described in Section 11.1
30
–40 C
–40 C
0 C
(3)
T
T
T
A
A
A
32
+70 C (commercial)
+85 C (industrial)
+125 C (extended)
TBD
TBD
Min
31
34
Typ
1999 Microchip Technology Inc.
10
10
(1)
32
100*
Max
25**
25**
Units
ns
ns
ns
ns
ns

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