PIC12C509A-04/P Microchip Technology Inc., PIC12C509A-04/P Datasheet - Page 31

• Manufacturer Part Number: PIC12C509A-04/P
• Description: 8 PIN, 1.5 KB OTP, 41 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12C509A-04/P

• Cpu Speed: 1 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 5
• Memory Capacity: 1024 Bytes
• Memory Type: OTP
• Number Of Bits: 8
• Number Of Leads: 6
• Package Type: 8-pin PDIP
• Programmable Memory: 1.5K Bytes
• Ram Size: 41 Bytes
• Speed: 4 MHz
• Timers: 1-8-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.0.2
This SCL input is used to synchronize the data transfer
from and to the device.
7.1
The following bus protocol is to be used with the
EEPROM data memory.
• Data transfer may be initiated only when the bus
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 7-3).
7.1.1
Both data and clock lines remain HIGH.
7.1.2
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
7.1.3
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
is not busy.
1999 Microchip Technology Inc.
SERIAL CLOCK
BUS CHARACTERISTICS
BUS NOT BUSY (A)
START DATA TRANSFER (B)
STOP DATA TRANSFER (C)
7.1.4
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
7.1.5
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 7-4).
Note:
DATA VALID (D)
ACKNOWLEDGE
Acknowledge bits are not generated if an
internal programming cycle is in progress.
PIC12C5XX
DS40139E-page 31
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