PIC16F1827-I/SS Microchip Technology Inc., PIC16F1827-I/SS Datasheet - Page 279
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PIC16F1827-I/SS
Manufacturer Part Number
PIC16F1827-I/SS
Description
20 SSOP .209in TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhance
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16F1827-I/SS
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SSOP
Programmable Memory
7K Bytes
Ram Size
384 Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Standby Current (pic16lf182x)
30 nA @ 1.8 V, Typical
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1827-I/SS
Manufacturer:
NELL
Quantity:
45
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REGISTER 25-1:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0/0
SMP
SMP: SPI Data Input Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I
1 = Enable input logic so that thresholds are compliant with SM bus™ specification
0 = Disable SM bus™ specific inputs
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
(I
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
S: Start bit
(I
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
In I
1 = Read
0 = Write
In I
1 = Transmit is in progress
0 = Transmit is not in progress
UA: Update Address bit (10-bit I
1 = Indicates that the user needs to update the address in the SSPxADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPxBUF is full
0 = Receive not complete, SSPxBUF is empty
Transmit (I
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty
2
2
C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)
C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)
2
2
2
2
R/W-0/0
C Master or Slave mode:
C™ mode only:
C Slave mode:
C Master mode:
CKE
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode.
SSPxSTAT: SSPx STATUS REGISTER
2
C mode only):
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
2
C modes):
R-0/0
D/A
2
C mode only)
2
C mode only)
2
C mode only)
R-0/0
P
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R-0/0
S
PIC16(L)F1826/27
R-0/0
R/W
R-0/0
UA
DS41391D-page 279
R-0/0
BF
bit 0
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