PIC16F1827-I/SS Microchip Technology Inc., PIC16F1827-I/SS Datasheet - Page 260
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PIC16F1827-I/SS
Manufacturer Part Number
PIC16F1827-I/SS
Description
20 SSOP .209in TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhance
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16F1827-I/SS
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SSOP
Programmable Memory
7K Bytes
Ram Size
384 Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Standby Current (pic16lf182x)
30 nA @ 1.8 V, Typical
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
PIC16F1827-I/SS
Manufacturer:
NELL
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PIC16(L)F1826/27
25.5.6
Clock stretching occurs when a device on the bus
holds the SCLx line low effectively pausing communi-
cation. The slave may stretch the clock to allow more
time to handle data or prepare a response for the mas-
ter device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and han-
dled by the hardware that generates SCLx.
The CKP bit of the SSPxCON1 register is used to con-
trol stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCLx line to go
low and then hold it. Setting CKP will release SCLx
and allow more communication.
25.5.6.1
Following an ACK if the R/W bit of SSPxSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPxBUF with data to
transfer to the master. If the SEN bit of SSPxCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
FIGURE 25-23:
DS41391D-page 260
WR
SSPxCON1
SDAx
SCLx
CKP
Note 1: The BF bit has no effect on if the clock will
CLOCK STRETCHING
2: Previous versions of the module did not
Normal Clock Stretching
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSPxBUF was read before the 9th falling
edge of SCLx.
stretch the clock for a transmission if
SSPxBUF was loaded before the 9th fall-
ing edge of SCLx. It is now always cleared
for read requests.
CLOCK SYNCHRONIZATION TIMING
DX
Master device
asserts clock
25.5.6.2
In 10-bit Addressing mode, when the UA bit is set, the
clock is always stretched. This is the only time the
SCLx is stretched without CKP being cleared. SCLx is
released immediately after a write to SSPxADD.
25.5.6.3
When AHEN bit of SSPxCON3 is set; CKP is cleared
by hardware after the 8th falling edge of SCLx for a
received matching address byte. When DHEN bit of
SSPxCON3 is set; CKP is cleared after the 8th falling
edge of SCLx for received data.
Stretching after the 8th falling edge of SCLx allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
25.5.7
Any time the CKP bit is cleared, the module will wait
for the SCLx line to go low and then hold it. However,
clearing the CKP bit will not assert the SCLx output
low until the SCLx output is already sampled low.
Therefore, the CKP bit will not assert the SCLx line
until an external I
asserted the SCLx line. The SCLx output will remain
low until the CKP bit is set and all other devices on the
I
to the CKP bit will not violate the minimum high time
requirement for SCLx (see
2
Master device
releases clock
C bus have released SCLx. This ensures that a write
Note: Previous versions of the module did not
CLOCK SYNCHRONIZATION AND
THE CKP BIT
stretch the clock if the second address byte
did not match.
10-bit Addressing Mode
Byte NACKing
2
C master device has already
2011 Microchip Technology Inc.
Figure
25-22).
DX ‚
–
1
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