MAX3984UTE+ Maxim Integrated Products, MAX3984UTE+ Datasheet - Page 5

• Manufacturer Part Number: MAX3984UTE+
• Description: IC PREMP DRIVER 1CH 16-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Driverr

Specifications of MAX3984UTE+

• Number Of Drivers/receivers: 1/0
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: Input range selection is IN_LEV = logic-low. Residual deterministic jitter is the difference between the source jitter at point
Note 11: Measured with 101010… pattern at 10Gbps with less than 1in of FR-4 at the input.
Note 12: True open-collector outputs. V
LOS Open-Collector Current
Sink
LOS Response Time
(Note 4)
LOS Transition Time
CONTROL INPUTS: TX_DISABLE, PE0, PE1, OUT_LEV, IN_LEV
Logic-High Voltage
Logic-Low Voltage
Logic-High Current
Logic-Low Current
CC
= +3.0V to +3.6V, T
PARAMETER
Supply voltage to reach 90% of final value in less than 100µs, but not less than 10µs. Power-on delay interval measured
from the 50% level of the final voltage at the filter’s device side to 50% level of final current. The supply is to remain at or
above 3V for at least 100ms. Only one full-scale transition is permitted during this interval. Aberrations on the transition are
limited to less than 100mV.
IN+ and IN- are single-ended, 50Ω terminations to (V
Load is 50Ω ±1% at each side and the pattern is 0000011111 or equivalent pattern at 2.5Gbps.
Guaranteed by design and characterization.
PE1 = PE0 = logic-high (maximum preemphasis), load is 50Ω ±1% at each side. The pattern is 11001100 (50% edge den-
sity) at 10Gbps. AC common-mode output is computed as:
where:
V
V
AC common-mode voltage (V
DC common-mode voltage (V
Using 0000011111 or equivalent pattern at 2.5Gbps. PE0 = PE1 = logic-low for minimum preemphasis. Measured within
2in of the output pins with Rogers 4350 dielectric, or equivalent, and ≥ 10-mil line width. For transition time, the 0% refer-
ence is the steady state level after four zeros, just before the transition, and the 100% reference level is the steady state
level after four consecutive logic ones.
Pattern is 0000011111 or equivalent pattern at 10Gbps and 100mV
PE1 = logic-low for minimum preemphasis. Signal transition time is controlled by the 4th-order BT filter (7.5GHz band-
width) or equivalent. See Figure 3 for setup.
Test pattern (464 bits): 100 zeros, 1010, PRBS7, 100 ones, 0101, PRBS7.
Input range selection is IN_LEV = logic-high for FR-4 input equalization. Cables are unequalized, Amphenol Spectra-Strip
(160-2499-997) 24 AWG or equivalent. Residual deterministic jitter is the difference between the source jitter at point A
and the load jitter point D in Figure 2. The deterministic jitter (DJ) at the output of the transmission line must be from media
induced loss and not from clock source modulation. DJ is measured at point D of Figure 2.
A and the load jitter point D in Figure 3. The deterministic jitter (DJ) at the output of the transmission line must be from
media induced loss and not from clock source modulation. DJ is measured at point D of Figure 3.
P
N
= time-domain voltage measured at OUT+ with at least 10GHz bandwidth.
= time-domain voltage measured at OUT- with at least 10GHz bandwidth.
1Gbps to 10Gbps Preemphasis Driver with
_______________________________________________________________________________________
A
= 0°C to +85°C. Typical values are at T
SYMBOL
V
V
I
I
ACCM_RMS
DCCM
IH
IL
CC
IH
IL
= 0 and the external 4.7kΩ pullup resistor is connected to +5.5V.
V
) = average DC voltage of (V
ACCM_RMS
LOS asserted
LOS asserted; V
(Note 12)
Time from V
or rising above assert level to 50% point of
LOS output transition
Rise time or fall time (10% to 90%);
pullup supply = 5.5V; external pullup
R
Current required to maintain logic-high state
at V
Current required to maintain logic-low state
at V
) expressed as an RMS value.
IH
IL
4.7k
< +0.8V
> +2.0V
= RMS[(V
IN
dropping below deassert level
CC
CONDITIONS
OL
A
- 1.5V) ±0.2V.
P
= +25°C, V
+ V
0.4V
N
) / 2) - V
P
+ V
P-P
CC
N
differential swing. IN_LEV = logic-low and PE0 =
) / 2.
DCCM
= +3.3V, unless otherwise noted.)
Receive Equalizer
]
MIN
1.0
2.0
0
0
TYP
200
MAX
-150
350
0.8
25
25
10
UNITS
mA
μA
μA
μA
μA
μs
ns
V
V
5