DSPIC30F2023-30I/PT Microchip Technology Inc., DSPIC30F2023-30I/PT Datasheet - Page 90
DSPIC30F2023-30I/PT
Manufacturer Part Number
DSPIC30F2023-30I/PT
Description
DSP, 16-Bit, 12KB Flash, 512 RAM, 35 I/O, TQFP-44
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F2023-30IPT.pdf
(286 pages)
Specifications of DSPIC30F2023-30I/PT
A/d Inputs
12-Channels, 10-Bit
Comparators
4
Cpu Speed
30 MIPS
Eeprom Memory
0 Bytes
Input Output
35
Interface
I2C/SPI/UART
Ios
35
Memory Type
Flash
Number Of Bits
16
Package Type
44-pin TQFP
Programmable Memory
12K Bytes
Ram Size
512 Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
3-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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dsPIC30F1010/202X
FIGURE 8-1:
8.1
The 16-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal T
increment the respective timer when the gate input sig-
nal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
8.2
The input clock (F
Timer, has a prescale option of 1:1, 1:8, 1:64, and
1:256
(T1CON<5:4>). The prescaler counter is cleared when
any of the following occurs:
• a write to the TMR1 register
• clearing of the TON bit (T1CON<15>)
• device Reset such as POR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.
DS70178C-page 88
selected
Timer Gate Operation
Timer Prescaler
T1IF
T1CK
Event Flag
OSC
by
/2 or external clock) to the 16-bit
16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)
TGATE
control
0
1
Reset
Equal
bits
Comparator x 16
TCKPS<1:0>
TMR1
PR1
CY
Preliminary
Q
Q
to
Gate
Sync
CK
T
D
CY
8.3
During CPU Sleep mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
• The TSYNC bit (T1CON<2>) is asserted to a logic
When all three conditions are true, the timer will
continue to count up to the period register and be reset
to 0x0000.
When a match between the timer and the period regis-
ter occurs, an interrupt can be generated, if the
respective timer interrupt enable bit is asserted.
TGATE
(TCS = 1) and
‘0’, which defines the external clock source as
asynchronous
Timer Operation During Sleep
Mode
1 X
0 1
0 0
TON
TSYNC
© 2006 Microchip Technology Inc.
0
1
TCKPS<1:0>
1, 8, 64, 256
Prescaler
Sync
2
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