GAL20RA10B-20LP Lattice, GAL20RA10B-20LP Datasheet - Page 6

• Manufacturer Part Number: GAL20RA10B-20LP
• Description: PLD; Programmable AND-Array Logic; 24-Pin PDIP; -0.5 to V; 75 mA; 0.8 V
• Manufacturer: Lattice

Specifications of GAL20RA10B-20LP

• Circuit Type: Advanced, Electrically Erasable
• Current, High Level Output: -3.2 mA
• Current, Low Level Output: 8 mA
• Current, Supply: 75 mA
• Function Type: 64-Bits
• Logic Function: Programmable
• Logic Type: CMOS
• Package Type: PDIP-24
• Propagation Delay Time, (high-to-low Level Output): 7.5 ns
• Propagation Delay Time, (low-to-high Level Output): 7.5 ns
• Special Features: High Speed, Tri-State
• Temperature, Operating, Range: 0 to +75 °C
• Temperature, Range, Operating Ambient: 0 to +75 °C
• Voltage, Input, High Level: (-0.5 V to +7 V) +1 V
• Voltage, Input, Low Level: 0.8 V
• Voltage, Output, High Level: 2.4 V
• Voltage, Output, Low Level: 0.5 V
• Voltage, Supply: 4.75 to 5.25 V

3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
f
Switching Test Conditions
Input Pulse Levels
Input Rise and
Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
f
max with External Feedback 1/(
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
LOGIC
ARRAY
t
su
-15/-20/-30
470
470
470
R
-7/-10
1
REGISTER
CLK
390
390
390
390
390
R
2ns 10% – 90%
3ns 10% – 90%
2
t
GND to 3.0V
t
See Figure
su+
co
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
9
FROM OUTPUT (O/Q)
UNDER TEST
Specifications GAL20RA10
*C
L
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
LOGIC
ARRAY
f
max with No Feedback
R
2
+5V
REGISTER
R
1
CLK
C *
L
TEST POINT