PIC18F4620-I/P Microchip Technology Inc., PIC18F4620-I/P Datasheet - Page 37

• Manufacturer Part Number: PIC18F4620-I/P
• Description: 40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 3-1:
FIGURE 3-2:
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator block
(either INTRC or INTOSC), there are no distinguishable
differences between PRI_RUN and RC_RUN modes
during execution. However, a clock switch delay will
occur during entry to and exit from RC_RUN mode.
Therefore, if the primary clock source is the internal
oscillator block, the use of RC_RUN mode is not
recommended.
 2004 Microchip Technology Inc.
Note 1: Clock transition typically occurs within 2-4 T
Peripheral
Program
Counter
T1OSI
OSC1
Clock
Clock
RC_RUN MODE
Note 1: T
CPU
CPU Clock
PLL Clock
Peripheral
Program
Counter
Output
T1OSI
OSC1
Clock
2: Clock transition typically occurs within 2-4 T
Q1
SCS1:SCS0 bits changed
Q2
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
OST
PC
Q3
= 1024 T
Q4
Q1
Q1
OSC
T
1
OST
; T
PLL
(1)
PC
Q2
2
= 2 ms (approx). These intervals are not shown to scale.
Clock Transition
PIC18F2525/2620/4525/4620
3
T
OSTS bit set
Q3
PLL
(1)
OSC
(1)
Q4
PC + 2
n-1
.
OSC
Q1
This mode is entered by setting the SCS1 bit to ‘1’.
Although it is ignored, it is recommended that the SCS0
bit also be cleared; this is to maintain software compat-
ibility with future devices. When the clock source is
switched to the INTOSC multiplexer (see Figure 3-3),
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
1
n
.
Transition
Note:
2
Clock
n-1 n
(2)
Q2
PC + 2
Caution should be used when modifying a
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
DD
Q3
/F
Q2
OSC
Q4
Q3 Q4
specifications are violated.
Q1
Q1
DD
PC + 4
Q2
Q2
is less than 3V, it is
PC + 4
DS39626B-page 35
Q3
Q3
DD
.