PIC18F4620-I/P Microchip Technology Inc., PIC18F4620-I/P Datasheet - Page 279
PIC18F4620-I/P
Manufacturer Part Number
PIC18F4620-I/P
Description
40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4620-IP.pdf
(390 pages)
Specifications of PIC18F4620-I/P
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
36
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
64K Bytes
Ram Size
4K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F4620-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F4620-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4620-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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BNC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If CARRY
If CARRY
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Carry
BNC
-128
if CARRY bit is ‘0’
(PC) + 2 + 2n
None
If the CARRY bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
=
=
n
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
127
0011
BNC
operation
Process
Process
Data
Data
PC
Q3
Q3
No
Jump
nnnn
Write to PC
operation
operation
PIC18F2525/2620/4525/4620
Q4
No
Q4
No
nnnn
Preliminary
BNN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If NEGATIVE =
If NEGATIVE =
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Negative
BNN
-128
if NEGATIVE bit is ‘0’
(PC) + 2 + 2n
None
If the NEGATIVE bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
Q2
No
‘n’
‘n’
=
=
=
n
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
127
0111
BNN
operation
Process
Process
Data
Data
PC
Q3
No
Q3
DS39626B-page 277
Jump
nnnn
Write to PC
operation
operation
Q4
No
Q4
No
nnnn
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