PIC18F4620-I/P Microchip Technology Inc., PIC18F4620-I/P Datasheet - Page 293
PIC18F4620-I/P
Manufacturer Part Number
PIC18F4620-I/P
Description
40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4620-IP.pdf
(390 pages)
Specifications of PIC18F4620-I/P
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
36
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
64K Bytes
Ram Size
4K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Price
Part Number:
PIC18F4620-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F4620-I/PT
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
PIC18F4620-I/PT
Manufacturer:
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Quantity:
20 000
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LFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
After Instruction
Decode
Decode
FSR2H
FSR2L
Q1
Read literal
Read literal
Load FSR
LFSR f, k
0
0
k
None
The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
2
2
‘k’ MSB
‘k’ LSB
LFSR 2, 3ABh
1110
1111
Q2
=
=
f
k
FSRf
2
4095
03h
ABh
1110
0000
Process
Process
Data
Data
Q3
k
00ff
7
kkk
‘k’ to FSRfL
Write literal
literal ‘k’
MSB to
PIC18F2525/2620/4525/4620
FSRfH
Write
k
Q4
kkkk
11
kkk
Preliminary
MOVF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
W
REG
W
Q1
register ‘f’
Move f
MOVF
0
d
a
f
N, Z
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
MOVF
Read
0101
Q2
=
=
=
=
f
[0,1]
[0,1]
dest
255
22h
FFh
22h
22h
f {,d {,a}}
REG, 0, 0
00da
Process
Data
Q3
DS39626B-page 291
95 (5Fh). See
ffff
Write W
Q4
ffff
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