DSPIC30F5011-30I/PT Microchip Technology Inc., DSPIC30F5011-30I/PT Datasheet - Page 29
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DSPIC30F5011-30I/PT
Manufacturer Part Number
DSPIC30F5011-30I/PT
Description
16 BIT MCU/DSP 64LD 30MIPS 66 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F5011-30IPT.pdf
(224 pages)
Specifications of DSPIC30F5011-30I/PT
A/d Inputs
16-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
52
Interface
CAN, I2C, SPI, UART/USART
Ios
52
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
66K Bytes
Ram Size
4K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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FIGURE 3-5:
3.2
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
© 2006 Microchip Technology Inc.
Data
Space
EA
Note:
Upper Half of Data
Space is Mapped
into Program Space
BSET
MOV
MOV
MOV
Data Address Space
16
EA<15> = 0
EA<15> = 1
CORCON,#2
#0x01, W0
W0, PSVPAG
0x8000, W0
PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines
the page in program space to which the upper half of data space is being mapped).
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
15
15
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Space
0x0000
0x8000
15
0xFFFF
Concatenation
Address
PSVPAG
0x01
3.2.1
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
8
dsPIC30F5011/5013
(1)
23
23
DATA SPACE MEMORY MAP
Program Space
15
Data Read
DS70116F-page 27
0
0x000100
0x008000
0x017FFF
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