DSPIC30F5011-30I/PT Microchip Technology Inc., DSPIC30F5011-30I/PT Datasheet - Page 133
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DSPIC30F5011-30I/PT
Manufacturer Part Number
DSPIC30F5011-30I/PT
Description
16 BIT MCU/DSP 64LD 30MIPS 66 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F5011-30IPT.pdf
(224 pages)
Specifications of DSPIC30F5011-30I/PT
A/d Inputs
16-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
52
Interface
CAN, I2C, SPI, UART/USART
Ios
52
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
66K Bytes
Ram Size
4K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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19.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the conver-
sion trigger. The SSRC bits provide for up to 4 alternate
sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under ADC clock control. The SAMC
bits select the number of ADC clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
19.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing until the next sampling trigger. The ADCBUF will
not be updated with the partially completed A/D conver-
sion sample. That is, the ADCBUF will continue to con-
tain the value of the last completed conversion (or the
last value written to the ADCBUF register).
If the clearing of the ADON bit coincides with an auto-
start, the clearing has a higher priority and a new
conversion will not start.
19.6
The ADC conversion requires 14 T
the ADC conversion clock is software selected, using a
six-bit counter. There are 64 possible options for T
EQUATION 19-1:
© 2006 Microchip Technology Inc.
Programming the Start of
Conversion Trigger
Aborting a Conversion
Selecting the ADC Conversion
Clock
T
AD
= T
CY
* (0.5*(ADCS<5:0> + 1))
CLOCK
ADC CONVERSION
AD
. The source of
AD
.
The internal RC oscillator is selected by setting the
ADRC bit.
For correct ADC conversions, the ADC conversion
clock (T
time of 334 nsec (for V
Specifications section for minimum T
operating conditions.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 19-1:
Since,
Sampling Time = Acquisition Time + Conversion Time
Therefore,
Sampling Rate =
If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’
dsPIC30F5011/5013
Therefore,
Set ADCS<5:0> = 19
AD
ADCS<5:0> = 2
Minimum T
) must be selected to ensure a minimum T
Actual T
= ~200 kHz
= 1 T
= 15 x 334 nsec
AD
T
(15 x 334 nsec)
AD
CY
=
AD
= 2 •
= 19
=
= 334 nsec
ADC CONVERSION
CLOCK AND SAMPLING
RATE CALCULATION
DD
= 334 nsec
= 33.33 nsec (30 MIPS)
+ 14 T
T
33.33 nsec
1
= 5V). Refer to the Electrical
T
T
CY
2
AD
33.33 nsec
CY
334 nsec
2
(ADCS<5:0> + 1)
AD
– 1
DS70116F-page 131
(19 + 1)
AD
– 1
under other
AD
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