DS90CF364AMTD/NOPB National Semiconductor, DS90CF364AMTD/NOPB Datasheet - Page 3

• Manufacturer Part Number: DS90CF364AMTD/NOPB
• Description: IC RCVR LVDS FPD 18BIT 48-TSSOP
• Manufacturer: National Semiconductor
• Type: Driverr

Specifications of DS90CF364AMTD/NOPB

• Number Of Drivers/receivers: 1/0
• Protocol: RS644
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Number Of Drivers: 21
• Number Of Receivers: 3
• Data Rate: 1300 Mbps
• Operating Supply Voltage: 3.3 V
• Maximum Power Dissipation: 1890 mW
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current: 60mA
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: TSSOP
• No. Of Pins: 48
• Operating Temperature Range: -10°C To +70°C
• Msl: MSL 2 - 1 Year
• Bandwidth: 170GHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS90CF364AMTD; *DS90CF364AMTD/NOPB; DS90CF364AMTD

CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Symbol
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the DS90C383B transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). The RSKM will change when different
transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less
than 250 ps).
CMOS/TTL Low-to-High Transition Time
CMOS/TTL High-to-Low Transition Time
Receiver Input Strobe Position for Bit 0
Figure 12
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
Receiver Input Strobe Position for Bit 0
Figure 12
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin
RxCLK OUT Period
RxCLK OUT High Time
RxCLK OUT Low Time
RxOUT Setup to RxCLK OUT
RxOUT Hold to RxCLK OUT
RxCLK IN to RxCLK OUT Delay @ 25°C, V
Receiver Phase Lock Loop Set
Receiver Power Down Delay
OD
and ΔV
)
)
OD
).
(Note
CC
(Figure
= 3.3V and T
(Figure
(Figure 5
4)
5)
(Figure 13
(Figure 5
(Figure 10
(Figure 5
Parameter
5)
(Figure 7
A
)
= +25C.
)
)
)
(Figure
(Figure
)
)
(Figure 4
(Figure 4
CC
= 3.3V
11,
11,
)
)
3
(Figure 6
f = 25 MHz
f = 65 MHz
f = 25 MHz
f = 65 MHz
f = 65 MHz
)
12.62
18.33
24.04
29.75
35.46
1.20
6.91
11.7
13.9
Min
750
500
0.7
2.9
5.1
7.3
9.5
5.0
5.0
4.5
4.0
3.5
15
13.38
19.09
24.80
30.51
36.22
1.96
7.67
12.1
14.3
Typ
1.8
1.1
3.3
5.5
7.7
9.9
7.6
6.3
7.3
6.3
5.0
2
T
14.24
19.95
25.66
31.37
37.08
Max
2.82
8.53
10.2
12.4
14.6
1.4
3.6
5.8
8.0
9.0
9.0
7.5
50
10
5
5
1
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Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
μs