STSMIA832TBR STMicroelectronics, STSMIA832TBR Datasheet - Page 8

• Manufacturer Part Number: STSMIA832TBR
• Description: IC LINE RCVR 1.8V/2.8V 25-TFBGA
• Manufacturer: STMicroelectronics
• Type: Receiverr

Specifications of STSMIA832TBR

• Number Of Drivers/receivers: 0/1
• Protocol: SMIA
• Voltage - Supply: 2.65 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 25-µTFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5147-2

Pin configuration
Figure 7.
Table 2.
1. X = channel number 0 to 7.
8/25
Logical Channels
Name
SOL
EOL
SOF
EOF
In the beginning of frame and in the end of frame, line synchronization codes are replaced
by the frame synchronization codes. Synchronization signal usage is shown in figure 7
below. Bit order of the synchronization codes is the same as for data, byte-wise LSB first.
CCP2 synchronization codes
The purpose of logical channels is to separate different data flows, which are interleaved in
the data stream.
The DMA channel identifier number is directly encoded in the 4-byte CCP embedded sync
codes. The CCP receiver will monitor the DMA channel identifier and de-multiplex the
interleaved video streams to their appropriate DMA channel. A maximum of 8 data streams
is supported. Valid channel identifiers are 0 to 7.
Synchronization codes as per SMIA specifications
FFH 00H 00H 0XH (to) FFH 00H 00H 7XH
Synchronization codes
FFH 00H 00H X0H
FFH 00H 00H X1H
FFH 00H 00H X2H
FFH 00H 00H X3H
Doc ID 12174 Rev 5
Line Start Code
Line End Code
Frame Start Code
Frame End Code
DMA Channel Identifier from Channel 0 to 7
(1)
Notes
STSMIA832