STSMIA832TBR STMicroelectronics, STSMIA832TBR Datasheet - Page 6

• Manufacturer Part Number: STSMIA832TBR
• Description: IC LINE RCVR 1.8V/2.8V 25-TFBGA
• Manufacturer: STMicroelectronics
• Type: Receiverr

Specifications of STSMIA832TBR

• Number Of Drivers/receivers: 0/1
• Protocol: SMIA
• Voltage - Supply: 2.65 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 25-µTFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5147-2

Pin configuration
2.2
Figure 4.
6/25
V
Both the camera sensor module and the baseband processor interface operate at
V
Supplementary notes: SMIA specification
The standard mobile imaging architecture (SMIA) specification defines an interface between
the digital camera module and mobile phone engine. It defines a standard data transmission
and control interface between transmitter (camera module) and receiver (mobile phone
engine). The data transmission interface (referred to as CCP2) is a unidirectional differential
serial interface with data and clock/strobe signals. The physical layer of CCP2 is based on
signaling scheme called SubLVDS, which is current mode differential low voltage signaling
method modified from the IEEE 1596.3 LVDS standard for reduced power consumption.
STSMIA832 operates in a data/strobe signaling mode. The use of data-strobe coding
together with SubLVDS enables the use of high data rates with low EMI.
Data/clock signaling
Data is a differential output from camera module. Data format is in most of cases bytewise
(i.e. on 8-bit boundary) least significant bit (LSB) first. When nothing is being transferred, the
DATA lines remain high, except in power shutdown. Figure 4 illustrates the bytewise LSB
first transmission.
Data clock signaling
Clock is a differential signal, output from camera module. The receiver reads the data on
rising edge of the CCP_CLK. The clock signal may be free running or gated. For most cases
free running clock is preferred due to simpler implementation in the transmitting end.
However, in some cases gated clock may be better solution. If gated transmission clock is
used, clock remains high when nothing is being transferred, except in power shutdown.
Data/strobe signaling
The data-strobe coding consists of two parallel signals, data and strobe. The data signal
carries the bit-serial data while the strobe signal state toggles whenever data signal does
not change state. Thus, either the data signal or the strobe signal changes between two
data bits. If both signals change simultaneously it is interpreted as an error. The signaling
method is presented in the
The benefit of using data-strobe signaling is that there is no need for transferring continuous
clock over the CCP2 bus. The frequency of the bus is also divided by two. The clock is
reconstructed at the receiving end from the data and strobe signals. This simplifies the EMC
design and in addition, EMI is reduced compared to normal data/clock signaling.
L
DD
= 1.8 V. The subLVDS receiver core operating voltage is V
, V
L
Figure 5
Doc ID 12174 Rev 5
below.
DD
= 2.8 V typical.
STSMIA832