AD9958BCPZ Analog Devices Inc, AD9958BCPZ Datasheet - Page 40

• Manufacturer Part Number: AD9958BCPZ
• Description: IC DDS DUAL 500MSPS DAC 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9958BCPZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) Phase Coherent FSK Modulator (CN0186)
• Resolution (bits): 10 b
• Master Fclk: 500MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Pll Type: Frequency Synthesis
• Frequency: 500MHz
• Supply Current: 105mA
• Supply Voltage Range: 1.71V To 1.89V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 56
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9958/PCBZ - BOARD EVALUATION FOR AD9958
• Lead Free Status / Rohs Status: Compliant

AD9958
Bit
6
5
4
3:2
1
0
Function Register 2 (FR2)—Address 0x02
Two bytes are assigned to this register. The FR2 is used to control the various functions, features, and modes of the AD9958.
Table 33. Bit Descriptions for FR2
Bit
15
14
13
12
11:8
7
6
5
4
3: 2
1:0
Mnemonic
External power-down mode
SYNC_CLK disable
DAC reference power-down
Open
Manual hardware sync
Manual software sync
Mnemonic
All channels autoclear sweep
accumulator
All channels clear
sweep accumulator
All channels autoclear phase
accumulator
All channels clear phase
Accumulator
Open
Auto sync enable
Multidevice sync master enable
Multidevice sync status
Multidevice sync mask
Open
System clock offset
Description
0 = the external power-down mode is in fast recovery power-down mode (default). In this mode,
when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered
down.
1 = the external power-down mode is in full power-down mode. In this mode, when the
PWR_DWN_CTL input pin is high, all functions are powered down. This includes the DAC and PLL,
which take a significant amount of time to power up.
0 = the SYNC_CLK pin is active (default).
1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive logic is
shut down. However, the synchronization circuitry remains active internally to maintain normal
device operation.
0 = DAC reference is enabled (default).
1 = DAC reference is powered down.
See the Synchronizing Multiple AD9958 Devices section for details.
0 = the manual hardware synchronization feature of multiple devices is inactive (default).
1 = the manual hardware synchronization feature of multiple devices is active.
1 = the manual software synchronization feature of multiple devices is active. See the
Synchronizing Multiple AD9958 Devices section for details.
Description
0 = a new delta word is applied to the input, as in normal operation, but not loaded into the
accumulator (default).
1 = this bit automatically and synchronously clears (loads 0s into) the sweep accumulator for one
cycle upon reception of the I/O_UPDATE sequence indicator on both channels.
0 = the sweep accumulator functions as normal (default).
1 = the sweep accumulator memory elements for both channels are asynchronously cleared.
0 = a new frequency tuning word is applied to the inputs of the phase accumulator, but not
loaded into the accumulator (default).
1 = this bit automatically and synchronously clears (loads 0s into) the phase accumulator for one
cycle upon receipt of the I/O update sequence indicator on both channels.
0 = the phase accumulator functions as normal (default).
1 = the phase accumulator memory elements for both channels are asynchronously cleared.
See the Synchronizing Multiple AD9958 Devices section for more details.
See the Synchronizing Multiple AD9958 Devices section for more details.
See the Synchronizing Multiple AD9958 Devices section for more details.
0 = the manual software synchronization feature of multiple devices is inactive (default).
See the Synchronizing Multiple AD9958 Devices section for more details.
See the Synchronizing Multiple AD9958 Devices section for more details.
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