AD9953YSVZ Analog Devices Inc, AD9953YSVZ Datasheet - Page 19

• Manufacturer Part Number: AD9953YSVZ
• Description: IC DDS DAC 14BIT 400MSPS 48-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9953YSVZ

• Resolution (bits): 14 b
• Master Fclk: 400MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Data Rate: 25Mbps
• Rf Ic Case Style: TQFP
• No. Of Pins: 48
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465V
• Operating Temperature Range: -40°C To +105°C
• Msl: MSL 3 - 168 Hours
• Frequency Max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9953/PCB - BOARD EVAL FOR AD9953
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

input of the phase accumulator and supplies the frequency
tuning word(s) for the device. When the RAM output drives the
phase accumulator, the phase offset word (POW, Addres
drives the phase-offset adder. Similarly, when the RAM out
drives the phase offset adder, the frequency tuning word (FT
Address 0x04) drives the phase accumulator. When CFR1<31>
is Logic 0, the RAM is inactive unless being written to via the
serial port. The power-up state of the AD9953 is the single-tone
mode, in which the RAM enable bit is inactive. The RAM is
segmented into four unique slices controlled by the Profile<1:0
input pins.
All RAM writes/reads, unless otherwise specified, are cont
by the Profile<1:0> input pins and the respective RAM segm
control word. The RAM can be written to during normal
operation, but any I/O operation that commands the RAM to be
written immediately suspends read operation from the RA
causing the current mode of operation to be nonfunctional. Thi
excludes single-tone mode, as the RAM is not read in this mode
Writing the RAM is accomplished as follows. After configuring
the desired RAM segment control words, the desired RAM
segment must be selected via the profile sele
During the instruction byte, write the address for the RAM,
0x0B. The serial port and RAM controller will work in
conjunction to determine the width of the profile and the ser
port will accept the defined number of 32-bit words
sequentially from the beginning address
Consider the following example:
•
•
•
The RAM controller would configur
256 32-
and sent to RAM Address 256. The next 32 bits would be pars
and sent to 257, and so forth, all the way through until the 256
word was sent (grand total of 8,192 data bits in this operatio
MODES OF OPERATION
Single-Tone Mode
In single-tone mode, the DDS core uses a single tuning word.
Whatever value is stored in FTW0 is supplied to the phase
accumulator. This value can only be changed manually, which is
done by writing a new value to FTW0 and by issuing an I/O
UPDATE. Phase adjustment is possible through the ph
offset registe
The RAM Segment Control Word 1 lists the beginning
RAM address at 256 and the ending address at 511.
PS0 = 1 and PS1 = 0.
The instruction byte is 10001001.
bit words. The first 32 bits would be parsed as a word
r.
e the serial port to expect
to the ending address.
ct pins PS<1:0>.
ase
s 0x05)
rolled
M,
ent
put
n).
Rev. A | Page 19 of 32
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ial
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RAM Controlled Modes of Operation
Direct Switch Mode
Direct switch mode enables FSK or PSK modulation. The
AD9953 is programmed for direct switch mode by writing the
RAM enable bit true and programming the RAM segment
mode control bits of each desired profile to Logic 000(b). This
mode simply reads the RAM contents at the RAM segment
beginning address for the current profile. No address ramping is
enabled in direct switch mode.
To perform 4
c
address value. In addition, the RAM enable bit is written true,
which enables the RAM, and the RAM destination bit is written
false, setting the RAM output to be the frequency tuning word.
The Profile<1:0> inputs are the 4-tone FSK data inputs. When
the profile is changed, the frequency tuning word stored in the
new profile is loaded into the phase accumulator and is used to
increment the currently stored value in a phase continuous
fashion. The phase offset word drives the phase-offset adder.
Two-tone FSK is accomplished by using only one profile pin f
data.
Programming the AD9953 for PSK modulation is similar to
FSK except the RAM destination bit is set to a Logic 1, enabling
the RAM output to drive the phase offset adder. The FTW0
drives the input to the phase accumulator. Toggling the profile
pins changes (modulates) the current phase value. The upper
14 bits of the RAM drive the phas
Bit <17:0> of the RAM output are unused when the RAM
dest
sw ch mode.
Ra p-Up Mode
Ramp-up mode, in conjunction with the segmented RAM
capability, allows up to four different sweep profiles to be
programmed into the AD9953. The AD9953 is programmed for
ramp-up mode by writing the RAM enable bit true and
programming the RAM mode control bits of each profile to be
used to Logic 001(b). As in all m
the RAM destination
drives the phase accum
Upon starting a sweep (via an I/O UPDATE or change in
profile bits), the RAM address generator loads the RAM
segment beginning address bits of the current RSCW, driving
the RAM output from this address, and the ramp rate timer
loads the RAM segment address ramp rate bits. When the
ramp rate time
in
ra
c
a
c
ontrol word for direct switch mode and a unique beginning
ontinues until the RAM address generator has incremented to
n address equal to the RAM segment final address bits of the
urrent RSCW.
crements to the next address and the timer reloads the ramp
te bits and begins a new countdown cycle. This sequence
it
s
m
ination bit is set. The no-dwell bit is a Don’t Care in d
-tone FSK, the user programs each RAM segment
r finishes a cycle, the RAM address generator
bit controls whether the RAM output
ulator or the phase offset adder.
odes that enable the memory,
e adder (<31:18>).
AD9953
irect
or