DP83934CVUL-33 National Semiconductor, DP83934CVUL-33 Datasheet - Page 48

• Manufacturer Part Number: DP83934CVUL-33
• Description: IC CTRLR ORIENT NETWORK 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL-33

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83934CVUL-33

6 0 SONIC-T Registers
6 3 6 Interrupt Status Register
(RA
This register (Figure 6-9) indicates the source of an interrupt when the INT pin goes active Enabling the corresponding bits in
the IMR allows bits in this register to produce an interrupt When an interrupt is active one or more bits in this register are set to
a ‘‘1’’ A bit is cleared by writing ‘‘1’’ to it Writing a ‘‘0’’ to any bit has no effect
This register is cleared by a hardware reset and unaffected by a software reset
Bit
15
14
13
12
11
10
9
r w
k
15
0
5 0
e
read write
l
r w
BR
14
Must be 0
BR BUS RETRY OCCURRED
Indicates that a Bus Retry (BRT) operation has occurred In Latched Bus Retry mode (LBR in the DCR) BR will only
be set when the SONIC-T is a bus master Before the SONIC-T will continue any DMA operations BR must be
cleared In Unlatched mode the BR bit should be cleared also but the SONIC-T will not wait for BR to be cleared
before requesting the bus again and continuing its DMA operations (See Sections 6 3 2 and 7 3 6 for more
information on Bus Retry )
HBL CD HEARTBEAT LOST
If the transceiver fails to provide a collision pulse (heart beat) during the first 6 4 s of the Interframe Gap after
transmission this bit is set
LCD LOAD CAM DONE
Indicates that the Load CAM command has finished writing to all programmed locations in the CAM
(See Section 6 1 1 )
PINT PROGRAMMED INTERRUPT
Indicates that upon reading the TXpkt config field the SONIC-T has detected the PINT bit to be set
(See Section 6 3 4 )
PKTRX PACKET RECEIVED
Indicates that a packet has been received and been buffered to memory This bit is set after the RXpkt seq no field
is written to memory
TXDN TRANSMISSION DONE
Indicates that either (1) there are no remaining packets to be transmitted in the Transmit Descriptor Area (i e the
EOL bit has been detected as a ‘‘1’’) (2) the Halt Transmit command has been given (HTX bit in CR is set to a ‘‘1’’)
or (3) a transmit abort condition has occurred This condition occurs when any of following bits in the TCR are set
BCM EXC FU or EXD This bit is set after the TXpkt status field has been written to
e
5h)
HBL
r w
13
LCD
r w
12
PINT
r w
11
BR
HBL
LCD
PINT
PKTRX
TXDN
TXER
TC
RDE
RBE
RBAE
CRC
FAE
MP
RFO
Field
(Continued)
PKTRX
r w
10
FIGURE 6-9 Interrupt Status Register
BUS RETRY OCCURRED
CD HEARTBEAT LOST
LOAD CAM DONE
PROGRAMMABLE INTERRUPT
PACKET RECEIVED
TRANSMISSION DONE
TRANSMIT ERROR
TIMER COMPLETE
RECEIVE DISCRIPTORS EXHAUSTED
RECEIVE BUFFERS EXHAUSTED
RECEIVE BUFFER AREA EXCEEDED
CRC TALLY COUNTER ROLLOVER
FRAME ALIGNMENT ERROR
MISSED PACKET COUNTER ROLLOVER
RECEIVE FIFO OVERRUN
PTDN
r w
9
TXER
r w
8
48
Description
Meaning
r w
TC
7
RDE
r w
6
RBE
r w
5
RBAE
r w
4
CRC
r w
3
FAE
r w
2
r w
MP
1
RFO
r w
0