PC8477BV-1 National Semiconductor, PC8477BV-1 Datasheet - Page 12

• Manufacturer Part Number: PC8477BV-1
• Description: IC ADVANCED FLOPPY CTRLR 68PLCC
• Manufacturer: National Semiconductor
• Series: SuperFDC™r

Specifications of PC8477BV-1

• Controller Type: Floppy Disk Controller
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *PC8477BV-1

3 0 Register Description
D5
D4–D2
D1 –D0
Note FM mode is not guaranteed through functional testing
3 7 DATA REGISTER (FIFO) Read Write
The FIFO (read write) is used to transfer all commands
data and status between the P and the PC8477B During
the Command Phase the P writes the command bytes into
the FIFO after polling the RQM and DIO bits in the MSR
During the Result Phase the P reads the result bytes from
the FIFO after polling the RQM and DIO bits in the MSR
The enabling of the FIFO and setting of the FIFO threshold
is done via the Configure command If the FIFO is enabled
PRECOMP
Data Rate Select
Data Rate
TABLE 3-5 Default Precompensation Delays
500 kb s
300 kb s
250 kb s
1
1
0
0
1
TABLE 3-4 Write Precompensation Delays
4 3 2
1 1 1
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
0 0 0
1 Mb s
TABLE 3-6 Data Rate Select Encoding
Undefined Should be set to 0
Precompensation Select These three bits se-
lect the amount of write precompensation the
floppy controller will use on the WDATA disk
interface output Table 3-4 shows the amount of
precompensation used for each bit pattern In
most cases the default values (Table 3-5) can
be used however alternate values can be cho-
sen for specific types of drives and media
Track 0 is the default starting track number for
precompensation The starting track number
can be changed in the Configure command
Data Rate Select 1 0 These bits determine the
data rate for the floppy controller See Table 3-6
for the corresponding data rate for each value
of D1 D0 The data rate select bits are unaffect-
ed by a software reset and are set to 250 kb s
after a hardware reset
2
1
0
1
0
Precompensation Delay
Precompensation Delay
500 kb s
300 kb s
250 kb s
1 Mb s
MFM
DEFAULT
125 0 ns
125 0 ns
125 0 ns
125 0 ns
166 7 ns
208 3 ns
250 0 ns
41 7 ns
41 7 ns
83 3 ns
Data Rate
0 0 ns
(Continued)
250 kb s
150 kb s
125 kb s
FM
Illegal
12
only the Execution Phase byte transfers use the 16 byte
FIFO The FIFO is always disabled during the Command
and Result Phases of a controller operation If the FIFO is
enabled it will not be disabled after a software reset if the
LOCK bit is set in the Lock Command After a hardware
reset the FIFO is disabled to maintain compatibility with PC-
AT systems
The 16 byte FIFO can be used for DMA Interrupt or soft-
ware polling type transfers during the execution of a read
write format or scan command In addition the FIFO can
be put into a Burst or Non-Burst mode with the Mode com-
mand In the Burst mode DRQ or INT remains active until
all of the bytes have been transferred to or from the FIFO In
the Non-Burst mode DRQ or INT is deasserted for 350 ns
to allow higher priority transfer requests to be serviced The
Mode command can also disable the FIFO for either reads
or writes separately The FIFO allows the system a larger
latency without causing a disk overrun underrun error Typi-
cal uses of the FIFO would be at the 1 Mb s data rate or
with multi-tasking operating systems The default state of
the FIFO is disabled with a threshold of zero The default
state is entered after a hardware reset
During the Execution Phase of a command involving data
transfer to from the FIFO the system must respond to a
data transfer service request based on the following formu-
la
This formula is good for all data rates with the FIFO enabled
or disabled THRESH is a four bit value programmed in the
Configure command which sets the FIFO threshold If the
FIFO is disabled THRESH is zero in the above formula The
last term of the formula (16
to the microcode overhead required by the PC8477B This
delay is also data rate dependent See Table 6-1 for the
t
The programmable FIFO threshold (THRESH) is useful in
adjusting the floppy controller to the speed of the system In
other words a slow system with a sluggish DMA transfer
capability would use a high value of THRESH giving the
system more time to respond to a data transfer service re-
quest (DRQ for DMA mode or INT for Interrupt mode) Con-
versely a fast system with quick response to a data transfer
service request would use a low value of THRESH
3 8 DIGITAL INPUT REGISTER (DIR) Read Only
This diagnostic register is used to detect the state of the
DSKCHG disk interface input and some diagnostic signals
The function of this register depends on the register mode
of operation When in the PC-AT mode the D6– D0 are
TRI-STATE to avoid conflict with the fixed disk status regis-
ter at the same address The DIR is unaffected by a soft-
ware reset
DRP
RESET
COND
DESC
Maximum Allowable Data Transfer Service Time
and t
(THRESH
ICP
D7
times
D6
Data Register (FIFO)
a
1)
D5
c
8
c
c
Byte Mode
Data 7 0
D4
t
ICP
t
DRP
) is an inherent delay due
D3
b
(16
D2
c
t
ICP
D1
)
D0