PC8477BV-1 National Semiconductor, PC8477BV-1 Datasheet - Page 11

• Manufacturer Part Number: PC8477BV-1
• Description: IC ADVANCED FLOPPY CTRLR 68PLCC
• Manufacturer: National Semiconductor
• Series: SuperFDC™r

Specifications of PC8477BV-1

• Controller Type: Floppy Disk Controller
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *PC8477BV-1

3 0 Register Description
3 4 DRIVE REGISTER (TDR) Read Write
This register is used to assign a particular drive number with
the tape drive support mode of the data separator All other
logical drives are assigned floppy drive support with the
data separator Any future reference to the assigned tape
drive will invoke tape drive support The TDR is unaffected
by a software reset
TDR
D7 –D2
D1 –D0
3 5 MAIN STATUS REGISTER (MSR) Read Only
The read only Main Status Register indicates the current
status of the disk controller The Main Status Register is
always available to be read One of its functions is to control
the flow of data to and from the Data Register (FIFO) The
Main Status Register indicates when the disk controller is
ready to send or receive data through the Data Register It
should be read before each byte is transferred to or from
the Data Register except during a DMA transfer No delay is
required when reading this register after a data transfer
After a hardware or software reset or recovery from a pow-
er down state the Main Status Register is immediately avail-
able to be read by the P It will contain a value of 00 hex
until the oscillator circuit has stabilized and the internal reg-
isters have been initialized When the PC8477B is ready to
receive a new command it will report an 80 hex to the P
The system software can poll the MSR until it is ready The
worst case time allowed for the MSR to report an 80 hex
value (RQM set) is 2 5 s after reset or power up
MSR
RESET
RESET
COND
DESC
COND
DESC
TAPESEL1
TABLE 3-3 Tape Drive Assignment Values
RQM DIO NON CMD DRV3 DRV2 DRV1 DRV0
0
0
1
1
N A N A N A N A N A N A
D7
D7
0
X
Reserved These bits are ignored when written
to and are TRI-STATE when read
Tape Select 1 0 These two bits assign a logical
drive number to be a tape drive Drive 0 is not
available as a tape drive and is reserved as the
floppy disk boot drive See Table 3-3 for the
tape drive assignment values
D6
0
D6
X
DMA PROG BUSY BUSY BUSY BUSY
D5
0
D5
X
TAPESEL0
D4
0
D4
0
1
0
1
X
D3
D3
0
X
D2
X
D2
(Continued)
0
SELECTED
TAPE TAPE
SEL1 SEL0
DRIVE
None
D1
0
D1
0
1
2
3
D0
D0
0
0
11
D7
D6
D5
D4
D3
D2
D1
D0
3 6 DATA RATE SELECT REGISTER (DSR) Write Only
This write only register is used to program the data rate
amount of write precompensation power down mode and
software reset The data rate is programmed via the CCR
not the DSR for PC-AT and PS 2 Model 30 and MicroChan-
nel applications Other applications can set the data rate in
the DSR The data rate of the floppy controller is deter-
mined by the most recent write to either the DSR or CCR
The DSR is unaffected by a software reset A hardware re-
set will set the DSR to 02 (hex) which corresponds to the
default precompensation setting and 250 kb s
DSR
D7
D6
RESET
COND
DESC
RESET PWR
S W LOW
D7
0
Request for Master Indicates that the control-
ler is ready to send or receive data from the P
through the FIFO This bit is cleared immediate-
ly after a byte transfer and will become set
again as soon as the disk controller is ready for
the next byte During a Non-DMA Execution
phase the RQM indicates the status of the in-
terrupt pin
Data I O (Direction) Indicates whether the
controller is expecting a byte to be written to (0)
or read from (1) the Data Register
Non-DMA Execution Indicates that the con-
troller is in the Execution Phase of a byte trans-
fer operation in the Non-DMA mode Used for
multiple byte transfers by the
tion Phase through interrupts or software poll-
ing
Command in Progress This bit is set after the
first byte of the Command Phase is written This
bit is cleared after the last byte of the Result
Phase is read If there is no Result Phase in a
command the bit is cleared after the last byte
of the Command Phase is written
Drive 3 Busy Set after the last byte of the
Command Phase of a Seek or Recalibrate com-
mand is issued for drive 3 Cleared after reading
the first byte in the Result Phase of the Sense
Interrupt Command for this drive
Drive 2 Busy Same as above for drive 2
Drive 1 Busy Same as above for drive 1
Drive 0 Busy Same as above for drive 0
Software Reset A 1 in this bit location will re-
set the part similar to the DOR RESET (D2) ex-
cept that this software reset is self-clearing
Low Power A 1 to this bit will put the controller
into the Manual Low Power mode The oscilla-
tor and data separator circuits will be turned off
Manual Low Power can also be accessed via
the Mode command The chip will come out of
low power after a software reset or access to
the Data Register or Main Status Register
D6 D5
0
0
0
COMP2 COMP1 COMP0
PRE-
D4
0
PRE-
D3
0
PRE-
D2
0
DRATE1 DRATE0
P in the Execu-
D1
1
D0
0