CY7C63833-LFXC Cypress Semiconductor Corp, CY7C63833-LFXC Datasheet - Page 8

• Manufacturer Part Number: CY7C63833-LFXC
• Description: IC USB PERIPHERAL CTRLR 32VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63833-LFXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-2258; CY7C63833-LFXC

7. CPU Registers
The CPU registers in enCoRe II devices are in two banks with 256 registers in each bank. Bit[4]/XIO bit in the CPU Flags register
must be set/cleared to select between the two register banks
7.1 Flags Register
The Flags Register is set or reset only with logical instruction.
Table 7-1. CPU Flags Register (CPU_F) [R/W]
Table 7-2. CPU Accumulator Register (CPU_A)
Document 38-08035 Rev. *K
Bit [7:5]: Reserved
Bit 4: XIO
Set by the user to select between the register banks
0 = Bank 0
1 = Bank 1
Bit 3: Super
Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user.)
0 = User Code
1 = Supervisor Code
Bit 2: Carry
Set by the CPU to indicate whether there has been a carry in the previous logical/arithmetic operation.
0 = No Carry
1 = Carry
Bit 1: Zero
Set by the CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation.
0 = Not Equal to Zero
1 = Equal to Zero
Bit 0: Global IE
Determines whether all interrupts are enabled or disabled
0 = Disabled
1 = Enabled
Note CPU_F register is only readable with the explicit register address 0xF7. The OR F, expr and AND F, expr instructions must
be used to set and clear the CPU_F bits.
Bit [7:0]: CPU Accumulator [7:0]
8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
7
–
0
7
–
0
Reserved
6
–
0
6
–
0
5
–
0
5
–
0
Table 7-1
CPU Accumulator [7:0]
R/W
XIO
4
0
4
–
0
on page 8
Super
R
3
0
3
–
0
Carry
RW
CY7C63310, CY7C638xx
2
0
2
–
0
Zero
RW
1
1
1
–
0
Global IE
RW
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0
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