CY7C63833-LFXC Cypress Semiconductor Corp, CY7C63833-LFXC Datasheet - Page 64

• Manufacturer Part Number: CY7C63833-LFXC
• Description: IC USB PERIPHERAL CTRLR 32VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63833-LFXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-2258; CY7C63833-LFXC

23. Details of Mode for Differing Traffic Conditions
24. Register Summary
The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF.
Document 38-08035 Rev. *K
NAK IN
Mode
Control Endpoint
1101
1100
1100
0A–0B
SIE
07–09
11–13
Addr
0C
0D
0E
0F
00
01
02
03
04
05
06
10
14
15
16
20
21
22
23
24
25
26
27
28
29
Token
OUT
IN
IN
FRTMRH
FRTMRL
TCAP0R
TCAP1R
P0DATA
P1DATA
P2DATA
P3DATA
P4DATA
P02CR–
P05CR–
P14CR–
TCAP0F
TCAP1F
PITMRH
PITMRL
P00CR
P01CR
P04CR
P06CR
P07CR
P10CR
P11CR
P12CR
P13CR
P16CR
P17CR
Name
P2CR
P3CR
PIRL
PIRH
Count
Bus Event
x
x
x
Reserved
Reserved Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPI Use
Output
Output
Output
P0.7
P1.7
CLK
CLK
TIO
7
Dval
x
x
x
P0.6/TIO1 P0.5/TIO0 P0.4/INT2
P1.6/SMI
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
SO
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
6
D0/1 Response S
Reserved
Reserved
x
x
x
Res
P1.5/SMO
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
SI
5
STALL
NAK
SIE
Res
Res
TTL Thresh Reserved
TTL Thresh Reserved
TTL Thresh Reserved
TTL Thresh Reserved
TTL Thresh Reserved
TTL Thresh Reserved
TTL Thresh High Sink
TTL Thresh Reserved
TTL Thresh Reserved
P1.4/SCLK P1.3/SSEL P1.2/VREG
3.3V Drive
3.3V Drive
Free Running Timer [15:8]
Free Running Timer [7:0]
Prog Interval Timer [7:0]
Capture 0 Falling [7:0]
Capture 1 Falling [7:0]
Capture 0 Rising [7:0]
Capture 1 Rising [7:0]
EP0 Mode Register
4
Prog Interval [7:0]
Reserved
I O A MODE DTOG
P0.3/INT1
High Sink
High Sink
Reserved
3
Prog Interval Timer [11:8]
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
P0.2/INT0
Prog Interval [11:8]
2
(continued)
EP0 Count Register
Res
P0.1/CLK-
up Enable
Reserved
PS/2 Pull
P1.1/D–
DVAL COUNT FIFO
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Pull up
Pull up
Pull up
Pull up
Pull up
Pull up
Pull up
Pull up
Pull up
Pull up
Pull up
OUT
1
P2.1–P2.0
P3.1–P3.0
P0.0/CLKI
P1.0/D+
CY7C63310, CY7C638xx
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
N
0
EP0
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
-bbbbbbb
-bbbbbbb
-bbbbbbb
-bbbbbbb
-bbbbbbb
-bbbbbbb
--bbbbbb
----bbbb
-bb---bb
-bb--b-b
----bbbb
----bbbb
If Enabled NAK IN
Interrupt
R/W
Stall IN
Ignore
Comments
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Default
Page 64 of 83
[+] Feedback
[+] Feedback