CY7C63833-LFXC Cypress Semiconductor Corp, CY7C63833-LFXC Datasheet - Page 70

• Manufacturer Part Number: CY7C63833-LFXC
• Description: IC USB PERIPHERAL CTRLR 32VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63833-LFXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-2258; CY7C63833-LFXC

28. AC Characteristics
Document 38-08035 Rev. *K
Note
USB Driver
T
T
T
T
T
V
USB Data Timing
T
T
T
T
T
T
T
T
T
T
T
GPIO Timing
T
T
SPI Timing
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Parameter
Non-USB Mode Driver Characteristics
10. In Master mode, first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.
R1
R2
F1
F2
R
CRS
DRATE
DJR1
DJR2
DEOP
EOPR1
EOPR2
EOPT
UDJ1
UDJ2
LST
FPS2
R_GPIO
F_GPIO
SMCK
SSCK
SCKH
SCKL
MDO
MDO1
MSU
MHD
SSU
SHD
SDO
SDO1
SSS
SSH
Transition Rise Time
Transition Rise Time
Transition Fall Time
Transition Fall Time
Rise/Fall Time Matching
Output Signal Crossover Voltage
Low Speed Data Rate
Receiver Data Jitter Tolerance
Receiver Data Jitter Tolerance
Differential to EOP Transition Skew
EOP Width at Receiver
EOP Width at Receiver
Source EOP Width
Differential Driver Jitter
Differential Driver Jitter
Width of SE0 during Diff. Transition
SDATA/SCK Transition Fall Time
Output Rise Time
Output Fall Time
SPI Master Clock Rate
SPI Slave Clock Rate
SPI Clock High Time
SPI Clock Low Time
Master Data Output Time
Master Data Output Time,
First bit with CPHA = 0
Master Input Data Setup time
Master Input Data Hold time
Slave Input Data Setup Time
Slave Input Data Hold Time
Slave Data Output Time
Slave Data Output Time,
First bit with CPHA = 0
Slave Select Setup Time
Slave Select Hold Time
Description
[8]
[8]
(continued)
[10]
C
C
C
C
Average Bit Rate (1.5 Mbps ± 1.5%)
To next transition
To pair transition
Rejects as EOP
Accept as EOP
To next transition
To pair transition
Measured between 10 and 90%
Vdd/Vreg with 50 pF load
Measured between 10 and 90%
Vdd/Vreg with 50 pF load
F
High for CPOL = 0, Low for CPOL = 1
Low for CPOL = 0, High for CPOL = 1
SCK to data valid
Time before leading SCK edge
SCK to data valid
Time after SS LOW to data valid
Before first SCK edge
After last SCK edge
CPUCLK
LOAD
LOAD
LOAD
LOAD
= 200 pF
= 600 pF
= 200 pF
= 600 pF
/6
Conditions
CY7C63310, CY7C638xx
1.4775
1.25
Min
–75
–45
–40
675
–95
–95
125
125
–25
100
150
150
1.3
75
75
80
50
50
50
50
50
Typical
1.5225
Max
300
300
125
100
330
210
300
100
100
2.0
1.5
2.2
75
45
95
95
50
15
50
2
Page 70 of 83
Mbps
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
V
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