CY7C68300B-56LFXC Cypress Semiconductor Corp, CY7C68300B-56LFXC Datasheet - Page 12

• Manufacturer Part Number: CY7C68300B-56LFXC
• Description: IC USB 2.0 BRIDGE BULK 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68300B-56LFXC

• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3.15 V ~ 3.45 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.10
This output controls the required host pull-up resistors on the
ATA interface. ATAPUEN is driven to ‘0’ when the ATA bus is
inactive. ATAPUEN is driven to ‘1’ when the ATA bus is active.
ATAPUEN is set to a Hi-Z state along with all other ATA
interface pins if VBUS_ATA_ENABLE is deasserted and the
ATA_EN functionality (EEPROM byte 8, bit 4) is enabled.
ATAPUEN can also be configured as an input. See Section 6.0
HID Functions for Button Controls
5.3.11
The AT2LP asserts PWR500# to indicate that VBUS current
may be drawn up to the limit specified by the bMaxPower field
of the USB configuration descriptors. In the 100-pin package,
PWR500# will only be asserted if VBUSPWRD and
DRVPWRVLD are also asserted. In the 56-pin package,
PWR500# only functions during bus-powered operation. If the
AT2LP enters a low-power state, PWR500# is deasserted.
When normal operation is resumed, PWR500# is restored
accordingly. Naturally, the PWR500# pin should never be used
to control power sources for the AT2LP. In the 68320 parts,
PWR500# can also be configured as an input. If the Drive
Power Valid Enable bit is set (EEPROM byte 8, bit 1),
PWR500# will ONLY be driven when Drive Power Valid is
active. See Section 6.0 HID Functions for Button Controls.
5.3.12
Some devices have the ability to be either self-powered or
bus-powered. The VBUSPWRD input pin enables these
devices to change between self-powered to bus-powered
modes by changing the contents of the bMaxPower field and
the self-powered bit in the configuration descriptor.
Note that current host drivers do not poll the device for this
information, so this pin is only effective on a USB or power-up
reset.
Table 5-3. Bus-Power Description
Table 6-1. EP1 Data Bitmap
Document 38-08033 Rev. *D
VBUSPWRD
bmAttributes
bMaxPower
PWR500#
7
value
bit 6
ATAPUEN
PWR500#
VBUSPWRD
6
1 when Config = 0
0 when Config = 1
250 (500mA)
5
EP1 Data Byte 1
1
0
4
1 (2mA) EEPROM value
3
0
1
1
2
1 when Config = 0
0 when Config = 1
EEPROM value
Not present
(56-pin)
used
used
1
0
5.3.13
Asserting RESET# for 10 ms will reset the entire chip. This pin
is normally tied to V
through a 0.1-µF capacitor, as shown in the figure below.
Cypress does not recommend an RC reset circuit for bus-
powered devices. See the application note EZ-USB
FX2
www.cypress.com for more information.
6.0
Cypress’ CY7C68320/CY7C68321 introduces the capability to
support Human Interface Device (HID) signaling to the host for
such functions as buttons. The ability to add buttons to a mass
storage solution opens new applications for backup and other
device-side notification to the host.
Optional HID functions can be added to the EEPROM
descriptors by setting bit 7 of byte 8 of the EEPROM to a value
of ‘1’. When this bit is set, several pins adopt alternate
functions for the 56-pin package. This allows the pins to be
used as button inputs. If there is a HID descriptor in the
EEPROM, these pins are polled by the hardware approxi-
mately every 17 ms. If a change is detected in the pin(s) state,
a report is sent via EP1. The report format for byte 0 and byte
1 are shown in Table 6-1.
7
™
/ AT2
RESET#
6
HID Functions for Button Controls
™
/ SX2
Figure 5-8. Typical Reset Circuit
CY7C68300B/CY7C68301B
5
™
100KΩ Ω Ω Ω
0.1µ µ µ µ F
CC
Reset and Power Considerations at
EP1 Data Byte 0
CY7C68320/CY7C68321
through a 100k resistor, and to GND
4
3
RESET#
2
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