CY7C68300B-56LFXC Cypress Semiconductor Corp, CY7C68300B-56LFXC Datasheet - Page 10

• Manufacturer Part Number: CY7C68300B-56LFXC
• Description: IC USB 2.0 BRIDGE BULK 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68300B-56LFXC

• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3.15 V ~ 3.45 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3
5.3.1
DPLUS and DMINUS are the USB signaling pins; they should
be tied to the D+ and D– pins of the USB connector. Because
they operate at high frequencies, the USB signals require
special consideration when designing the layout of the PCB.
See section 15.0 for PCB layout recommendations. When
RESET# is released, the internal pull-up on D+ is controlled
by VBUS_ATA_ENABLE. When VBUS_ATA_ENABLE is
HIGH, D+ is pulled up.
5.3.2
The clock and data pins for the I
to the configuration EEPROM and to 2.2K pull-up resistors tied
to V
seconds at start-up.
5.3.3
The AT2LP requires a 24-MHz (
internal timing. Typically, a 24-MHz (20-pF, 500-µW, parallel-
Table 5-2. USB Interrupt Pipe Data Bitmap
Document 38-08033 Rev. *D
7
CC
. The SCL and SDA pins are active for several milli-
Additional Pin Descriptions
DPLUS, DMINUS
SCL, SDA
XTALIN, XTALOUT
6
USB Interrupt Data Byte 1
5
4
12pF
2
C port should be connected
±
3
100ppm) signal to derive
XTALIN
Figure 5-6. XTALIN / XTALOUT Diagram
2
1
24MHz Xtal
0
resonant fundamental mode) crystal is used, but a 24-MHz
square wave from another source can also be used. If a crystal
is used, connect its pins to XTALIN and XTALOUT, and also
through 12-pF capacitors to GND as shown in Figure 5-6. If an
alternate clock source is used, apply it to XTALIN and leave
XTALOUT open.
5.3.4
The SYSIRQ pin provides a way for systems to request service
from host software by using the USB Interrupt pipe. If the
AT2LP has no pending interrupt data to return, USB interrupt
pipe data requests are NAKed. If pending data is available, the
AT2LP returns 16 bits of data; this data indicates the
HS_MODE signal (that indicates whether AT2LP is operating
in high-speed or full-speed), the VBUSPWRD pin, and the
GPIO pins. Table 5-2 gives the bitmap for the data returned on
the interrupt pipe and Figure 5-7 depicts the latching algorithm
incorporated by AT2LP.
The SYSIRQ pin must be tied low if the HID function is used
(refer to Section 6.0).
7
SYSIRQ
6
XTALOUT
USB Interrupt Data Byte 0
CY7C68300B/CY7C68301B
5
CY7C68320/CY7C68321
4
12pF
3
2
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