ENC28J60T/SO Microchip Technology, ENC28J60T/SO Datasheet - Page 95

• Manufacturer Part Number: ENC28J60T/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60T/SO

• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INDEX
B
Block Diagrams
Built-in Self-Test Controller ................................................. 75
C
Checksum Calculations ...................................................... 72
CLKOUT Pin ......................................................................... 6
Control Register Map .......................................................... 12
Control Register Summary............................................ 13–14
Control Registers ................................................................ 12
Customer Change Notification Service ............................... 91
Customer Notification Service............................................. 91
Customer Support ............................................................... 91
D
DMA Controller ................................................................... 71
Duplex Mode
E
Electrical Characteristics..................................................... 79
EREVID Register ................................................................ 22
Errata .................................................................................... 2
Ethernet Buffer .................................................................... 17
Ethernet Module
Ethernet Overview .............................................................. 31
© 2008 Microchip Technology Inc.
Crystal Oscillator Operation .......................................... 5
ENC28J60 Architecture ................................................ 3
Ethernet Buffer Organization ...................................... 18
Ethernet Termination and External
External Clock Source .................................................. 5
I/O Level Shifting Using 3-State Buffers ....................... 8
I/O Level Shifting Using AND Gates ............................. 8
Interrupt Logic ............................................................. 63
LEDB Polarity and Reset Configuration........................ 8
Magic Packet Format .................................................. 52
Memory Organization.................................................. 11
On-Chip Reset Circuit ................................................. 59
Pattern Match Filter Format ........................................ 51
Typical ENC28J60-Based Interface.............................. 4
Address Fill Mode ....................................................... 76
Associated Registers .................................................. 77
EBSTCS registers....................................................... 76
EBSTSD Register ....................................................... 76
Pattern Shift Fill Mode................................................. 76
Random Data Fill Mode .............................................. 76
Use.............................................................................. 76
Access to Buffers ........................................................ 17
Associated Registers .................................................. 72
Checksum Calculations .............................................. 72
Copying Memory......................................................... 71
Configuration and Negotiation .................................... 53
Absolute Maximum Ratings ........................................ 79
AC Characteristics ...................................................... 81
CLKOUT Pin AC ......................................................... 81
DC Characteristics ...................................................... 80
Oscillator Timing ......................................................... 81
Requirements for External Magnetics......................... 81
Reset AC..................................................................... 81
SPI Interface AC ......................................................... 82
Transmitting and Receiving Data
Connections .......................................................... 7
Receive Packet Layout ....................................... 43
Transmit Packet Layout ...................................... 40
Preliminary
F
Flow Control........................................................................ 55
Flowcharts
Full-Duplex Mode
H
Half-Duplex Mode
I
I/O Level Shifting .................................................................. 8
Initialization ......................................................................... 33
Interrupts ............................................................................ 63
L
LED Configuration ................................................................ 8
M
Magnetics and External Components................................... 7
Memory Organization ......................................................... 11
O
Oscillator............................................................................... 5
P
Packaging Information ........................................................ 83
Packet Format .................................................................... 31
Per Packet Control Byte Format ......................................... 39
PHID Registers ................................................................... 22
PHSTAT Registers ............................................................. 22
PHY Register Summary...................................................... 20
Associated Registers.................................................. 57
Full-Duplex Mode ....................................................... 55
Half-Duplex Mode....................................................... 55
Sample Full-Duplex Network (Diagram) ..................... 55
Receive Filters Using AND Logic ............................... 50
Receive Filters Using OR Logic.................................. 49
Operation.................................................................... 53
Operation.................................................................... 53
MAC Settings.............................................................. 34
PHY Settings .............................................................. 37
Receive Buffer ............................................................ 33
Receive Filters............................................................ 33
Transmit Buffer ........................................................... 33
Waiting for OST .......................................................... 33
DMA Flag (DMAIF) ..................................................... 69
INT Enable (INTIE) ..................................................... 64
Link Change Flag (LINKIF)......................................... 69
Receive Error Flag (RXERIF) ..................................... 68
Receive Packet Pending Flag (PKTIF) ....................... 69
Transmit Error Flag (TXERIF) .................................... 68
Transmit Interrupt Flag (TXIF) .................................... 68
Start-up Timer (OST).................................................... 5
Details......................................................................... 84
Marking....................................................................... 83
CRC Field ................................................................... 32
Data Field ................................................................... 32
Destination Address ................................................... 32
Padding Field.............................................................. 32
Preamble/Start-Of-Frame Delimiter............................ 31
Source Address .......................................................... 32
Type/Length Field....................................................... 32
ENC28J60
DS39662C-page 93