ENC28J60T/SO Microchip Technology, ENC28J60T/SO Datasheet - Page 44

• Manufacturer Part Number: ENC28J60T/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60T/SO

• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ENC28J60
TABLE 7-2:
DS39662C-page 42
EIE
EIR
ESTAT
ECON1
ETXSTL
ETXSTH
ETXNDL
ETXNDH
MACON1
MACON3
MACON4
MABBIPG
MAIPGL
MAIPGH
MACLCON1
MACLCON2
MAMXFLL
MAMXFLH
Legend:
Note 1:
Register
Name
— = unimplemented, r = reserved bit. Shaded cells are not used.
CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.
TX Start Low Byte (ETXST<7:0>)
TX End Low Byte (ETXND<7:0>)
Maximum Frame Length Low Byte (MAMXFL<7:0>)
Maximum Frame Length High Byte (MAMXFL<15:8>)
PADCFG2
TXRST
INTIE
Bit 7
INT
—
—
—
—
—
—
—
—
—
—
SUMMARY OF REGISTERS USED FOR PACKET TRANSMISSION
Back-to-Back Inter-Packet Gap (BBIPG<6:0>)
Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>)
Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>)
PADCFG1
BUFER
RXRST
DEFER
PKTIE
PKTIF
Bit 6
—
—
—
—
—
Collision Window (COLWIN<5:0>)
PADCFG0
DMAST
DMAIE
DMAIF
BPEN
Bit 5
—
—
—
—
r
TX Start High Byte (ETXST<12:8>)
TX End High Byte (ETXND<12:8>)
TXCRCEN
NOBKOFF
LATECOL
CSUMEN
Preliminary
LINKIE
LINKIF
Bit 4
—
r
Retransmission Maximum (RETMAX<3:0>)
PHDREN
TXPAUS
TXRTS
Bit 3
TXIE
TXIF
—
—
HFRMEN
RXBUSY
RXPAUS
RXEN
Bit 2
—
r
r
FRMLNEN
PASSALL
TXABRT
TXERIE
TXERIF
BSEL1
© 2008 Microchip Technology Inc.
Bit 1
r
CLKRDY
MARXEN
FULDPX
RXERIE
RXERIF
BSEL0
Bit 0
r
(1)
on page
Values
Reset
13
13
13
13
13
13
13
13
14
14
14
14
14
14
14
14
14
14