FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 77

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

Bit 0
This bit controls the Data Terminal Ready (nDTR) output.
forced to a logic "0". When bit 0 is a logic "0", the nDTR
output is forced to a logic "1".
Bit 1
This bit controls the Request To Send (nRTS) output. Bit
1 affects the nRTS output in a manner identical to that
described above for bit 0.
Bit 2
This bit controls the Output 1 (OUT1) bit. This bit does
not have an output pin and can only be read or written by
the CPU.
Bit 3
Output 2 (OUT2). This bit is used to enable an UART
interrupt.
interrupt output is forced to a high impedance state -
disabled.
interrupt outputs are enabled.
Bit 4
This bit provides the loopback feature for diagnostic
testing of the Serial Port. When bit 4 is set to logic "1",
the following occur:
1. The TXD is set to the Marking State(logic "1").
2. The receiver Serial Input (RXD) is disconnected.
3. The output of the Transmitter Shift Register is "looped
4. All MODEM Control inputs (nCTS, nDSR, nRI and
5. The four MODEM Control outputs (nDTR, nRTS,
6. The Modem Control output pins are forced inactive
7. Data that is transmitted is immediately received.
When bit 0 is set to a logic "1", the nDTR output is
back" into the Receiver Shift Register input.
nDCD) are disconnected.
OUT1 and OUT2) are internally connected to the
four MODEM Control inputs (nDSR, nCTS, RI and
DCD) respectively.
high.
When OUT2 is a logic "0", the serial port
When OUT2 is a logic "1", the serial port
77
This feature allows the processor to verify the transmit
and receive data paths of the Serial Port.
diagnostic mode, the receiver and the transmitter
interrupts are fully operational.
Interrupts are also operational but the interrupts' sources
are now the lower four bits of the MODEM Control
Register instead of the MODEM Control inputs. The
interrupts are still controlled by the Interrupt Enable
Register.
Bits 5 through 7
These bits are permanently set to logic zero.
LINE STATUS REGISTER (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
Bit 0
Data Ready (DR). It is set to a logic "1" whenever a
complete incoming character has been received and
transferred into the Receiver Buffer Register or the FIFO.
Receive Buffer Register or the FIFO.
Bit 1
Overrun Error (OE).
Receiver Buffer Register was not read before the next
character was transferred into the register, thereby
destroying the previous character. In FIFO mode, an
overrunn error will occur only when the FIFO is full and
the next character has been completely received in the
shift register, the character in the shift register is
overwritten but not transferred to the FIFO. The OE
indicator is set to a logic "1" immediately upon detection
of an overrun condition, and reset whenever the Line
Status Register is read.
Bit 2
Parity Error (PE). Bit 2 indicates that the received data
character does not have the correct even or odd parity, as
selected by the even parity select bit. The PE is set to a
logic "1" upon detection of a parity error and is reset to a
logic "0" whenever the Line Status Register is read. In
the FIFO mode this error is associated with the particular
character in the FIFO it applies to. This error is indicated
when the associated character is at the top of the FIFO.
Bit 3
Framing Error (FE).
character did not have a valid stop bit. Bit 3 is set to a
logic "1" whenever the stop bit following the last data bit
Bit 0 is reset to a logic "0" by reading all of the data in the
Bit 3 indicates that the received
Bit 1 indicates that data in the
The MODEM Control
In the