FDC37B727-NS SMSC, FDC37B727-NS Datasheet - Page 184

IC CTRLR SUPER I/O ENH 128-QFP

FDC37B727-NS

Manufacturer Part Number
FDC37B727-NS
Description
IC CTRLR SUPER I/O ENH 128-QFP
Manufacturer
SMSC
Datasheet

Specifications of FDC37B727-NS

Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
30mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1005

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Floppy Data Rate
Select Shadow
UART1 FIFO
Control Shadow
UART2 FIFO
Control Shadow
Forced Write Protect
Default = 0x00
on VTR POR
Ring Filter Select
NAME
REG INDEX
0xC6 R/W
0xC5 R/W
0xC2 R
0xC3 R
0xC4 R
the appropriate drive has been selected.
Bit[0] Force Change for FDC0
0=Inactive
1=Active
Bit[1] Force Change for FDC1
0=Inactive
1=Active
Bit[2:7] Reserved, Reads 0
Floppy Data Rate Select Shadow Register
Bit[7] Soft Reset
Bit[6] Power Down
Bit[5] Reserved
Bit[4] PRECOMP 2
Bit[3] PRECOMP 1
Bit[2] PRECOMP 0
Bit[1] Data Rate Select 1
Bit[0] Data Rate Select 0
UART1 FIFO Control Shadow Register
Bit[7] RCVR Trigger MSB
Bit[6] RCVR Trigger LSB
Bit[5] Reserved
Bit[4] Reserved
Bit[3] DMA Mode Select
Bit[2] XMIT FIFO Reset
Bit[1] RCVR FIFO Reset
Bit[0] FIFO Enable
UART2 FIFO Control Shadow Register
Bit[7] RCVR Trigger MSB
Bit[6] RCVR Trigger LSB
Bit[5] Reserved
Bit[4] Reserved
Bit[3] DMA Mode Select
Bit[2] XMIT FIFO Reset
Bit[1] RCVR FIFO Reset
Bit[0] FIFO Enable
Force Write Protect function forces the FDD
nWRTPRT input active if the FORCE WRTPRT bit is
active. The Force Write Protect function applies to
the nWRTPRT pin in the FDD Interface as well as
the nWRTPRT pin in the Parallel Port FDC.
Bit[0] Force Write Protect bit FDD0
0 = Inactive (Default)
1 = Active “forces the FDD nWRTPRT input active
when the drive has been selected” Note 2
Bit[1:7] Reserved, reads 0.
This register is used to select the operation of the
185
DEFINITION
STATE
C

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